参数资料
型号: MCF5307FT90B
厂商: MOTOROLA INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 90 MHz, RISC PROCESSOR, PQFP208
封装: 28 X 28 MM, PLASTIC, QFP-208
文件页数: 12/30页
文件大小: 117K
代理商: MCF5307FT90B
2
MCF5307 Product Brief
MOTOROLA
Overview, Continued
ColdFire Architecture
Provides New Price/
Performance Levels
The revolutionary ColdFire microprocessor architecture gives cost-sensitive,
high-volume markets new levels of price and performance. Based on the
concept of variable-length RISC technology, ColdFire combines the
architectural simplicity of conventional 32-bit RISC with a memory-saving,
variable-length instruction set. In dening the ColdFire architecture for
embedded processing applications, Motorola incorporated RISC architecture
for peak performance and a simplied version of the variable-length
instruction set found in the M68000 Family for code density.
Clock-Doubled
Version 3 Core Boosts
Performance
The MCF5307 is the rst of the ColdFire Family to contain the Version 3,
clock-doubled ColdFire microprocessor core. Increasing the internal speed of
the core allows higher performance while providing the system designer with
an easy-to-use external system interface.
ColdFire VL RISC
Offers Many
Advantages
By using a variable-length instruction set architecture, embedded system
designers using ColdFire RISC processors will enjoy signicant advantages
over conventional xed-length RISC architectures. The denser binary code for
ColdFire processors consumes less valuable memory than any xed-length
instruction set RISC processor available. This improved code density means
more efcient system memory use for a given application, and requires
slower, less costly memory to help achieve a target performance level.
The MCF5307
Integrates a Rich Set
of Modules with the
ColdFire V3 Core
The integrated peripheral functions provide high performance and exibility.
The DRAM controller can interface with up to 256 Mbytes of DRAM and
supports bursting, page-mode, EDO and synchronous DRAMs.
Serial communication channels are provided by two programmable full-
duplex UARTs and an M-Bus (I2C interface-compatible) module. Four
channels of DMA allow for fast data transfer using a programmable burst
mode independent of processor execution. The two 16-bit general-purpose
multimode timers provide separate input and output signals. For system
protection, the processor includes a programmable 16-bit software watchdog
timer. In addition, common system functions such as chip-selects, interrupt
control, bus arbitration, and an IEEE 1149.1 JTAG module are included.
A sophisticated debug interface supports background-debug mode and real-
time trace, with on-chip breakpoint registers accessible from an emulator or
the processor itself. This interface is present in all ColdFire-based processors
and allows common emulator support across the entire ColdFire Family.
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