
15-2
MCF5307 User’s Manual
Parallel Port Operation
15.1.2 Port A Data Direction Register (PADDR)
The PADDR determines the signal direction of each parallel port pin programmed as a
general-purpose I/O port in the PAR.
15.1.3 Port A Data Register (PADAT)
The PADAT value for inputs corresponds to the logic level at the pin; for outputs, the value
corresponds to the logic level driven onto the pin. Note the following:
PADAT has no effect on pins not congured for general-purpose I/O.
PADAT settings do not affect inputs. PADAT bit values determine the corresponding
logic levels of pins congured as outputs.
Table 15-1. Parallel Port Pin Descriptions
Pin
Description
PP[15:8]/
A[31:24]
MSB of the address bus/parallel port. Programmed through PAR[15–8]. If a PAR bit is 0, the associated
pin functions as a parallel port signal. If a bit is 1, the pin functions as an address bus signal. If all pins
are address signals, as much as 4 Gbytes of memory space are available.
TIP/PP7
Transfer-in-progress output/parallel port bit 7. Programmed through PAR[7]. Assertion indicates a bus
transfer is in progress; negation indicates an idle bus cycle if the bus is still granted to the processor.
Note that TIP is held asserted on back-to-back bus cycles.
DREQ[1:0]/
PP[6:5]
DMA request inputs/two bits of the parallel port. Programmed through PAR[6–5]. These inputs are
asserted by a peripheral device to request a DMA transfer.
TM[2:0]/
PP[4:2]]
Transfer type outputs/parallel port bits 4–2. Programmed through PAR[4–2]. For DMA transfers, these
signals provide acknowledge information. For emulation transfers, TM[2:0] indicate user or data transfer
types. For CPU space transfers, TM[2:0] are low. For interrupt acknowledge transfers, TM[2:0] carry the
interrupt level being acknowledged.
TT[1:0]/
PP[1:0]
Transfer type outputs/parallel port bits 1–0. Programmed through PAR[1–0].
When the MCF5307 is bus master, it outputs these signals. They indicate the current bus access type.
15
0
Field
PADDR
Reset
0000_0000_0000_0000
R/W
Address
Address MBAR + 0x244
Figure 15-2. Port A Data Direction Register (PADDR)
Table 15-2. PADDR Field Description
Bits
Name
Description
15–0
PADDR
Data direction bits. Each data direction bit selects the direction of the signal as follows:
0 Signal is dened as an input.
1 Signal is dened as an output.
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Freescale Semiconductor, Inc.
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