参数资料
型号: MCF5328CVM240
厂商: Freescale Semiconductor
文件页数: 30/50页
文件大小: 0K
描述: IC MCU 32BIT 240MHZ 256-MAPBGA
标准包装: 90
系列: MCF532x
核心处理器: Coldfire V3
芯体尺寸: 32-位
速度: 240MHz
连通性: EBI/EMI,以太网,I²C,SPI,SSI,UART/USART,USB,USB OTG
外围设备: DMA,LCD,PWM,WDT
输入/输出数: 94
程序存储器类型: ROMless
RAM 容量: 32K x 8
电压 - 电源 (Vcc/Vdd): 1.4 V ~ 3.6 V
振荡器型: 外部
工作温度: -40°C ~ 85°C
封装/外壳: 256-LBGA
包装: 托盘
MCF532x ColdFire Microprocessor Data Sheet, Rev. 5
Electrical Characteristics
Freescale Semiconductor
36
Table 22 lists specifications for the I2C output timing parameters shown in Figure 22.
Figure 22 shows timing for the values in Table 22 and Table 21.
Figure 22. I2C Input/Output Timings
I5
I2C_SCL/I2C_SDA fall time (VIH = 2.4 V to VIL =0.5 V)
1
ms
I6
Clock high time
4
tcyc
I7
Data setup time
0
ns
I8
Start condition setup time (for repeated start condition only)
2
tcyc
I9
Stop condition setup time
2
tcyc
Table 22. I2C Output Timing Specifications between SCL and SDA
Num
Characteristic
Min
Max
Units
I11
1 Output numbers depend on the value programmed into the IFDR; an IFDR programmed with the maximum
frequency (IFDR = 0x20) results in minimum output timings as shown in Table 22. The I2C interface is
designed to scale the actual data transition time to move it to the middle of the SCL low period. The actual
position is affected by the prescale and division values programmed into the IFDR; however, the numbers
given in Table 22 are minimum values.
Start condition hold time
6
tcyc
I2 1
Clock low period
10
tcyc
I3 2
2 Because I2C_SCL and I2C_SDA are open-collector-type outputs, which the processor can only actively drive
low, the time I2C_SCL or I2C_SDA take to reach a high level depends on external signal capacitance and
pull-up resistor values.
I2C_SCL/I2C_SDA rise time (VIL = 0.5 V to VIH =2.4 V)
s
I4 1
Data hold time
7
tcyc
I5 3
3 Specified at a nominal 50-pF load.
I2C_SCL/I2C_SDA fall time (VIH = 2.4 V to VIL = 0.5 V)
3
ns
I6 1
Clock high time
10
tcyc
I7 1
Data setup time
2
tcyc
I8 1
Start condition setup time (for repeated start condition only)
20
tcyc
I9 1
Stop condition setup time
10
tcyc
Table 21. I2C Input Timing Specifications between SCL and SDA (continued)
Num
Characteristic
Min
Max
Units
I2
I6
I1
I4
I7
I8
I9
I5
I3
I2C_SCL
I2C_SDA
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