参数资料
型号: MCF5482CZP166
厂商: Freescale Semiconductor
文件页数: 5/34页
文件大小: 0K
描述: IC MPU 32BIT COLDF 388-PBGA
标准包装: 40
系列: MCF548x
核心处理器: Coldfire V4E
芯体尺寸: 32-位
速度: 166MHz
连通性: CAN,EBI/EMI,以太网,I²C,SPI,UART/USART,USB
外围设备: DMA,PWM,WDT
输入/输出数: 99
程序存储器类型: ROMless
RAM 容量: 32K x 8
电压 - 电源 (Vcc/Vdd): 1.43 V ~ 1.58 V
振荡器型: 外部
工作温度: -40°C ~ 85°C
封装/外壳: 388-BBGA
包装: 托盘
FlexBus
MCF548x ColdFire Microprocessor, Rev. 4
Freescale Semiconductor
13
8.1
FlexBus AC Timing Characteristics
The following timing numbers indicate when data is latched or driven onto the external bus, relative to the system clock.
Table 10. FlexBus AC Timing Specifications
Num
Characteristic
Min
Max
Unit
Notes
Frequency of Operation
25
50
Mhz
1
1 The frequency of operation is the same as the PCI frequency of operation. The MCF548X supports a single
external reference clock (CLKIN). This signal defines the frequency of operation for FlexBus and PCI.
FB1
Clock Period (CLKIN)
20
40
ns
2
2 Max cycle rate is determined by CLKIN and how the user has the system PLL configured.
FB2
Address, Data, and Control Output Valid (AD[31:0], FBCS[5:0],
R/W, ALE, TSIZ[1:0], BE/BWE[3:0], OE, and TBST)
—7.0
ns
3
3 Timing for chip selects only applies to the FBCS[5:0] signals. Please see Section 9.2, “DDR SDRAM AC Timing
Characteristics” for SDCS[3:0] timing.
FB3
Address, Data, and Control Output Hold ((AD[31:0], FBCS[5:0],
R/W, ALE, TSIZ[1:0], BE/BWE[3:0], OE, and TBST)
1—
ns
3, 4
4 The FlexBus supports programming an extension of the address hold. Please consult the MCF548X
specification manual for more information.
FB4
Data Input Setup
3.5
ns
FB5
Data Input Hold
0
ns
FB6
Transfer Acknowledge (TA) Input Setup
4
ns
FB7
Transfer Acknowledge (TA) Input Hold
0
ns
FB8
Address Output Valid (PCIAD[31:0])
7.0
ns
5
5 These specs are used when the PCIAD[31:0] signals are configured as 32-bit, non-muxed FlexBus address
signals.
FB9
Address Output Hold (PCIAD[31:0])
0
ns
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