参数资料
型号: MCF5484CZP200
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 200 MHz, RISC PROCESSOR, PBGA388
封装: 27 X 27 MM, 1 MM PITCH, MS-034AAL-1, PBGA-388
文件页数: 7/34页
文件大小: 602K
代理商: MCF5484CZP200
SDRAM Bus
MCF548x ColdFire Microprocessor, Rev. 4
Freescale Semiconductor
15
Figure 12. FlexBus Write Timing
9
SDRAM Bus
The SDRAM controller supports accesses to main SDRAM memory from any internal master. It supports standard SDRAM or
double data rate (DDR) SDRAM, but it does not support both at the same time. The SDRAM controller uses SSTL2 and SSTL3
I/O drivers. Both SSTL drive modes are programmable for Class I or Class II drive strength.
9.1
SDR SDRAM AC Timing Characteristics
The following timing numbers indicate when data is latched or driven onto the external bus, relative to the memory bus clock,
when operating in SDR mode on write cycles and relative to SDR_DQS on read cycles. The MCF548x SDRAM controller is a
DDR controller that has an SDR mode. Because it is designed to support DDR, a DQS pulse must be supplied to the MCF548x
for each data beat of an SDR read. The MCF548x accomplishes this by asserting a signal called SDR_DQS during read cycles.
Care must be taken during board design to adhere to the following guidelines and specs with regard to the SDR_DQS signal
and its usage.
CLKIN
AD[X:0]
AD[31:Y]
R/W
ALE
TSIZ[1:0]
FBCSn, BE/BWEn
TA
FB1
A[X:0]
A[31:Y]
DATA
FB2
FB3
TSIZ[1:0]
FB3
FB6
FB7
OE
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相关代理商/技术参数
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MCF548X_07 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:MCF548x ColdFire㈢ Microprocessor