参数资料
| 型号： | MCH12140DR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 4/5页 |
| 文件大小： | 0K |
| 描述： | IC DETECTOR PHASE FREQ 8-SOIC |
| 标准包装： | 2,500 |
| 类型： | 相频探测器 |
| PLL： | 无 |
| 输入： | ECL |
| 输出： | ECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:2 |
| 差分 - 输入:输出： | 无/是 |
| 频率 - 最大： | 800MHz |
| 除法器/乘法器： | 无/无 |
| 电源电压： | 4.75 V ~ 5.5 V |
| 工作温度： | -40°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOICN |
| 包装： | 带卷 (TR) |
MCH12140, MCK12140
http://onsemi.com
4
APPLICATIONS INFORMATION
The 12140 is a high speed digital circuit used as a phase
comparator in an analog phase-locked loop. The device
determines the “lead” or “lag” phase relationship and time
difference between the leading edges of a VCO (V) signal
and a Reference (R) input. Since these edges occur only once
per cycle, the detector has a range of
±2p radians.
The operation of the 12140 can best be described using the
plots of Figure 2. Figure 2 plots the average value of U, D
and the difference between U and D versus the phase
difference between the V and R inputs.
There are four potential relationships between V and R: R
lags or leads V and the frequency of R is less than or greater
than the frequency of V. Under these four conditions the
12140 will function as follows:
Figure 2. Average Output Voltage vs. Phase Difference
VOH VOL
2
2p
pp
2p
U
Fv > Fr
R lags V
VOH
Fv < Fr
R leads V
VOH VOL
2
D
VOH
VOH VOL
2
UD
VOL VOH
2
2p
pp
2p
pp
2p
R lags V in phase
When the R and V inputs are equal in frequency and the
phase of R lags that of V the U output will stay HIGH while
the D output will pulse from HIGH to LOW. The magnitude
of the pulse will be proportional to the phase difference
between the V and R inputs reaching a minimum 50% duty
cycle under a 180
° out of phase condition. The signal on D
indicates to the VCO to decrease in frequency to bring the
loop into lock.
V frequency > R frequency
When the frequency of V is greater than that of R the
12140 behaves in a similar fashion as above. Again the
signal on D indicates that the VCO frequency must be
decreased to bring the loop into lock.
R leads V in phase
When the R and V inputs are equal in frequency and the
phase of R leads that of V the D output will stay HIGH while
the U output pulses from HIGH to LOW. The magnitude of
the pulse will be proportional to the phase difference
between the V and R inputs reaching a minimum 50% duty
cycle under a 180
° out of phase condition. The signal on U
indicates to the VCO to increase in frequency to bring the
loop into lock.
V frequency < R frequency
When the frequency of V is less than that of R the 12140
behaves in a similar fashion as above. Again the signal on U
indicates that the VCO frequency must be decreased to bring
the loop into lock.
From Figure 2 when V and R are at the same frequency and
in phase the value of U D is zero thus providing a zero error
voltage to the VCO. This situation indicates the loop is in lock
and the 12140 action will maintain the loop in its locked state.
ORDERING INFORMATION
Device
Package
Shipping
MCH12140D
SOIC8
98 Units / Rail
MCH12140DG
SOIC8
(PbFree)
98 Units / Rail
MCH12140DR2
SOIC8
2500 / Tape & Reel
MCH12140DR2G
SOIC8
(PbFree)
2500 / Tape & Reel
MCK12140D
SOIC8
98 Units / Rail
MCK12140DG
SOIC8
(PbFree)
98 Units / Rail
MCK12140DR2
SOIC8
2500 / Tape & Reel
MCK12140DR2G
SOIC8
(PbFree)
2500 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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