参数资料
型号: MCHRC705KJ1CPE
厂商: Freescale Semiconductor
文件页数: 66/108页
文件大小: 0K
描述: IC MCU 1.2K 4MHZ OTP 16-DIP
标准包装: 25
系列: HC05
核心处理器: HC05
芯体尺寸: 8-位
速度: 4MHz
外围设备: POR,WDT
输入/输出数: 10
程序存储器容量: 1.2KB(1.2K x 8)
程序存储器类型: OTP
RAM 容量: 64 x 8
电压 - 电源 (Vcc/Vdd): 3 V ~ 5.5 V
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 16-DIP(0.300",7.62mm)
包装: 管件
Low-Power Modes
MC68HC705KJ1 MC68HRC705KJ1 MC68HLC705KJ1 Data Sheet, Rev. 4.1
60
Freescale Semiconductor
6.3.5.1 STOP
The STOP instruction during EPROM programming clears the EPGM bit in the EPROM programming
register, removing the programming voltage from the EPROM.
6.3.5.2 WAIT
The WAIT instruction has no effect on EPROM/OTPROM operation.
6.4 Data-Retention Mode
In data-retention mode, the MCU retains RAM contents and CPU register contents at VDD voltages as low
as 2.0 Vdc. The data-retention feature allows the MCU to remain in a low power-consumption state during
which it retains data, but the CPU cannot execute instructions.
To put the MCU in data-retention mode:
1.
Drive the RESET pin to logic 0.
2.
Lower the VDD voltage. The RESET pin must remain low continuously during data-retention mode.
To take the MCU out of data-retention mode:
1.
Return VDD to normal operating voltage.
2.
Return the RESET pin to logic 1.
6.5 Timing
Figure 6-1. Stop Mode Recovery Timing
tILIH
OSCILLATOR STABILIZATION DELAY(5)
OSC
tRL
RESET
IRQ/VPP
INTERNAL
CLOCK
INTERNAL
ADDRESS
Notes:
1. Internal clocking from OSC1 pin
2. Edge-triggered external interrupt mask option
3. Edge- and level-triggered external interrupt mask option
4. Reset vector shown as example
RESET OR INTERRUPT
VECTOR FETCH
$07FE
$07FF
(NOTE 4)
BUS
(NOTE 3)
(NOTE 2)
(NOTE 1)
5. 4064 cycles or 128 cycles, depending on state of SOSCD bit in MOR
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