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型号： MCIMX31DVMN5DR2
厂商： Freescale Semiconductor
文件页数： 38/118页
文件大小： 0K
描述： IC MPU I.MX31 CONSUMR 473MAPBGA
标准包装： 750
系列： i.MX31
核心处理器： ARM11
芯体尺寸： 32-位
速度： 532MHz
连通性： 1 线，ATA，EBI/EMI，FIR，I²C，MMC/SD，PCMCIA，SIM，SPI，SSI，UART/USART，USB，USB OTG
外围设备： DMA，LCD，POR，PWM，WDT
程序存储器类型： ROMless
RAM 容量： 16K x 8
电压 - 电源 (Vcc/Vdd)： 1.22 V ~ 3.3 V
振荡器型： 外部
工作温度： 0°C ~ 70°C
封装/外壳： 473-LFBGA
包装： 带卷 (TR)
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
26
Freescale Semiconductor
Electrical Characteristics
4.3.5.1
Timing Parameters
In the timing equations, some timing parameters are used. These parameters depend on the implementation
of the ATA interface on silicon, the bus buffer used, the cable delay and cable skew. Table 23 shows ATA
timing parameters.
Table 23. ATA Timing Parameters
Name
Description
Value/
Contributing Factor1
1 Values provided where applicable.
T
Bus clock period (ipg_clk_ata)
peripheral clock
frequency
ti_ds
Set-up time ata_data to ata_iordy edge (UDMA-in only)
UDMA0
UDMA1
UDMA2, UDMA3
UDMA4
UDMA5
15 ns
10 ns
7 ns
5 ns
4 ns
ti_dh
Hold time ata_iordy edge to ata_data (UDMA-in only)
UDMA0, UDMA1, UDMA2, UDMA3, UDMA4
UDMA5
5.0 ns
4.6 ns
tco
Propagation delay bus clock L-to-H to
ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack, ata_data,
ata_buffer_en
12.0 ns
tsu
Set-up time ata_data to bus clock L-to-H
8.5 ns
tsui
Set-up time ata_iordy to bus clock H-to-L
8.5 ns
thi
Hold time ata_iordy to bus clock H to L
2.5 ns
tskew1
Max difference in propagation delay bus clock L-to-H to any of following signals
ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack, ata_data
(write), ata_buffer_en
7ns
tskew2
Max difference in buffer propagation delay for any of following signals
ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_dior, ata_diow, ata_dmack, ata_data
(write), ata_buffer_en
transceiver
tskew3
Max difference in buffer propagation delay for any of following signals ata_iordy, ata_data
(read)
transceiver
tbuf
Max buffer propagation delay
transceiver
tcable1
Cable propagation delay for ata_data
cable
tcable2
Cable propagation delay for control signals ata_dior, ata_diow, ata_iordy, ata_dmack
cable
tskew4
Max difference in cable propagation delay between ata_iordy and ata_data (read)
cable
tskew5
Max difference in cable propagation delay between (ata_dior, ata_diow, ata_dmack) and
ata_cs0, ata_cs1, ata_da2, ata_da1, ata_da0, ata_data(write)
cable
tskew6
Max difference in cable propagation delay without accounting for ground bounce
cable
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MCIMX31LC 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Multimedia Applications Processors for Industrial and Automotive Products
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MCIMX31LCVKN5C 功能描述:IC MPU MAP I.MX31L 457-MAPBGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - 微控制器， 系列:i.MX31 标准包装:1 系列:AVR® ATmega 核心处理器:AVR 芯体尺寸:8-位 速度:16MHz 连通性:I²C，SPI，UART/USART 外围设备:欠压检测/复位，POR，PWM，WDT 输入/输出数:32 程序存储器容量:32KB（16K x 16） 程序存储器类型:闪存 EEPROM 大小:1K x 8 RAM 容量:2K x 8 电压 - 电源 (Vcc/Vdd):2.7 V ~ 5.5 V 数据转换器:A/D 8x10b 振荡器型:内部 工作温度:-40°C ~ 125°C 封装/外壳:44-TQFP 包装:剪切带 (CT) 其它名称:ATMEGA324P-B15AZCT
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