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参数资料
型号： MCIMX31LCVMN4D
厂商： Freescale Semiconductor
文件页数： 67/108页
文件大小： 0K
描述： IC MPU I.MX31L AUTO 473MAPBGA
标准包装： 84
系列： i.MX31
核心处理器： ARM11
芯体尺寸： 32-位
速度： 400MHz
连通性： 1 线，ATA，EBI/EMI，FIR，I²C，MMC/SD，PCMCIA，SIM，SPI，SSI，UART/USART，USB，USB OTG
外围设备： DMA，LCD，POR，PWM，WDT
程序存储器类型： ROMless
RAM 容量： 16K x 8
电压 - 电源 (Vcc/Vdd)： 1.22 V ~ 3.3 V
振荡器型： 外部
工作温度： -40°C ~ 85°C
封装/外壳： 473-LFBGA
包装： 托盘
Electrical Characteristics
MCIMX31C/MCIMX31LC Technical Data, Rev. 4.3
Freescale Semiconductor
61
4.3.15.4.2
Interface to a TV Encoder, Electrical Characteristics
The timing characteristics of the TV encoder interface are identical to the synchronous display
characteristics. See Section 4.3.15.2.2, “Interface to Active Matrix TFT LCD Panels, Electrical
Characteristics” on page 55.
4.3.15.5
Asynchronous Interfaces
4.3.15.5.1
Parallel Interfaces, Functional Description
The IPU supports the following asynchronous parallel interfaces:
System 80 interface
— Type 1 (sampling with the chip select signal) with and without byte enable signals.
— Type 2 (sampling with the read and write signals) with and without byte enable signals.
System 68k interface
— Type 1 (sampling with the chip select signal) with or without byte enable signals.
— Type 2 (sampling with the read and write signals) with or without byte enable signals.
For each of four system interfaces, there are three burst modes:
1. Burst mode without a separate clock. The burst length is defined by the corresponding parameters
of the IDMAC (when data is transferred from the system memory) of by the HBURST signal
(when the MCU directly accesses the display via the slave AHB bus). For system 80 and system
68k type 1 interfaces, data is sampled by the CS signal and other control signals changes only when
transfer direction is changed during the burst. For type 2 interfaces, data is sampled by the WR/RD
signals (system 80) or by the ENABLE signal (system 68k) and the CS signal stays active during
the whole burst.
2. Burst mode with the separate clock DISPB_BCLK. In this mode, data is sampled with the
DISPB_BCLK clock. The CS signal stays active during whole burst transfer. Other controls are
changed simultaneously with data when the bus state (read, write or wait) is altered. The CS
signals and other controls move to non-active state after burst has been completed.
3. Single access mode. In this mode, slave AHB and DMA burst are broken to single accesses. The
data is sampled with CS or other controls according the interface type as described above. All
controls (including CS) become non-active for one display interface clock after each access. This
mode corresponds to the ATI single access mode.
Both system 80 and system 68k interfaces are supported for all described modes as depicted in Figure 51,
Figure 52, Figure 53, and Figure 54. These timing images correspond to active-low DISPB_D#_CS,
DISPB_D#_WR and DISPB_D#_RD signals.
Additionally, the IPU allows a programmable pause between two burst. The pause is defined in the
HSP_CLK cycles. It allows to avoid timing violation between two sequential bursts or two accesses to
different displays. The range of this pause is from 4 to 19 HSP_CLK cycles.
相关PDF资料
PDF描述
MCIMX31LCVMN4C IC MPU MAP I.MX31L 473-MAPBGA
VE-J5B-IX-S CONVERTER MOD DC/DC 95V 75W
VI-JNF-IX-S CONVERTER MOD DC/DC 72V 75W
VI-JND-IX-S CONVERTER MOD DC/DC 85V 75W
VI-J6P-IX-S CONVERTER MOD DC/DC 13.8V 75W
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