参数资料
型号: MCIMX351AJQ5C
厂商: Freescale Semiconductor
文件页数: 147/147页
文件大小: 0K
描述: MULTIMEDIA PROCESSOR 400-MAPBGA
标准包装: 90
系列: i.MX35
核心处理器: ARM11
芯体尺寸: 32-位
速度: 532MHz
连通性: 1 线,CAN,EBI/EMI,以太网,I²C,MMC,SPI,SSI,UART/USART,USB OTG
外围设备: DMA,I²S,LCD,POR,PWM,WDT
输入/输出数: 96
程序存储器类型: ROMless
RAM 容量: 128K x 8
电压 - 电源 (Vcc/Vdd): 1.33 V ~ 1.47 V
振荡器型: 外部
工作温度: -40°C ~ 85°C
封装/外壳: 400-LFBGA
包装: 托盘
i.MX35 Applications Processors for Automotive Products, Rev. 10
Freescale Semiconductor
99
4.9.16
1-Wire Timing Specifications
Figure 70 depicts the RPP timing, and Table 64 lists the RPP timing parameters.
Figure 70. Reset and Presence Pulses (RPP) Timing Diagram
MLBCLK high time
tmckh
9.7
9.3
10.6
10.2
ns
PLL unlocked
MLBCLK pulse width variation
tmpwv
——
0.7
ns pp
Note2
MLBSIG/MLBDAT input valid
to MLBCLK falling
tdsmcf
1—
ns
MLBSIG/MLBDAT input hold
from MLBCLK low
tdhmcf
0—
ns
MLBSIG/MLBDAT output high
impedance from MLBCLK low
tmcfdz
0—
tmckl
ns
Bus Hold Time
tmdzh
2—
ns
Note3
1 The MLB Controller can shut off MLBCLK to place MediaLB in a low-power state.
2 Pulse width variation is measured at 1.25 V by triggering on one edge of MLBCLK and measuring the spread on the other edge,
measured in ns peak-to-peak (pp)
3 The board must be designed to insure that the high-impedance bus does not leave the logic state of the final driven bit for this
time period. Therefore, coupling must be minimized while meeting the maximum capacitive load listed.
Table 64. RPP Sequence Delay Comparisons Timing Parameters
ID
Parameters
Symbol
Min.
Typ.
Max.
Units
OW1
Reset time low
tRSTL
480
511
s
OW2
Presence detect high
tPDH
15
60
s
OW3
Presence detect low
tPDL
60
240
s
OW4
Reset time high
tRSTH
480
512
s
Table 63. MLB Device 1024Fs Timing Parameters (continued)
Parameter
Symbol
Min
Typ
Max
Units
Comment
1-Wire bus
DS2502 Tx
“Presence Pulse”
(BATT_LINE)
1-WIRE Tx
“Reset Pulse”
OW1
OW2
OW3
OW4
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