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参数资料
| 型号： | MCM64PC64TSG66 |
| 厂商： | MOTOROLA INC |
| 元件分类： | DRAM |
| 英文描述： | 256K/512K Pipelined BurstRAM Secondary Cache Module for Pentium |
| 中文描述： | 64K X 64 CACHE TAG SRAM MODULE, 8 ns, DMA160 |
| 封装： | CARD EDGE MODULE-160 |
| 文件页数： | 13/16页 |
| 文件大小： | 167K |
| 代理商： | MCM64PC64TSG66 |
MCM64PC32T
MCM64PC64T
13
MOTOROLA FAST SRAM
TAG RAM WRITE CYCLE
(See Notes 1 and 2)
– 15
Parameter
Symbol
Min
Max
Unit
Notes
Write Cycle Time
tAVAV
tAVWL
tAVWH
tDVWH
tWHDX
tWLQZ
tWHQX
tWHAX
15
—
ns
3
Address Setup Time
0
—
ns
Address Valid to End of Write
12
—
ns
Data Valid to End of Write
7
—
ns
Data Hold Time
0
—
ns
Write Low to Output High–Z
0
7
ns
5,6,7
Write High to Output Active
4
—
ns
5,6,7
Write Recovery Time
0
—
ns
NOTES:
1. A write occurs when CWE is low.
2. If CG goes low coincident with or after CWE goes low, the output will remain in a high impedance state.
3. All timings are referenced from the last valid address to the first address transition.
4. If CG
≥
VIH, the output will remain in a high impedance state.
5. At any given voltage and temperature, tWLQZ (max) is less than tWHQX (min), both for a given device and from device to device.
6. Transition is measured
±
500 mV from steady–state voltage with load of Figure 3b.
7. This parameter is sampled and not 100% tested.
TAG RAM WRITE CYCLE
(See Notes 1 and 2)
DATA VALID
tDVWH
tAVWL
tAVWH
tAVAV
tWHAX
tWLWH
tWHDX
tWLQZ
tWHQX
HIGH Z
HIGH Z
AX (ADDRESS)
TWE
Q (DATA OUT)
D (DATA IN)
相关PDF资料 |
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| MCM6706J6 | Circular Connector; Body Material:Aluminum; Series:PT06; Number of Contacts:41; Connector Shell Size:20; Connecting Termination:Crimp; Circular Shell Style:Straight Plug; Circular Contact Gender:Socket; Insert Arrangement:20-41 |
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| MCM64PD32 | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:256K/512K Pipelined BurstRAM Secondary Cache Module for Pentium |
| MCM64PD32SG66 | 制造商:MOTOROLA 制造商全称:Motorola, Inc 功能描述:256K/512K Pipelined BurstRAM Secondary Cache Module for Pentium |
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