参数资料
型号: MCP16322T-500E/NG
厂商: Microchip Technology
文件页数: 22/34页
文件大小: 0K
描述: IC REG BUCK SYNC 5V 2A 16-VQFN
标准包装: 1
类型: 降压(降压)
输出类型: 固定
输出数: 1
输出电压: 5V
输入电压: 6 V ~ 24 V
PWM 型: 电流模式
频率 - 开关: 1MHz
电流 - 输出: 2A
同步整流器:
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 16-VFQFN 裸露焊盘
包装: 标准包装
供应商设备封装: 16-QFN(3x3)
其它名称: MCP16322T-500E/NGDKR
MCP16321/2
5.0.9 PCB LAYOUT INFORMATION
Good printed circuit board layout techniques are
important to any switching circuitry, and switching
power supplies are no different. When wiring the
switching high-current paths, short and wide traces
should be used. Therefore, it is important that the input
and output capacitors be placed as close as possible to
the MCP16321/2 to minimize the loop area.
The feedback resistors and feedback signal should be
routed away from the switching node and the switching
current loop. When possible, ground planes and traces
should be used to help shield the feedback signal and
minimize noise and magnetic interference.
A good MCP16321/2 layout starts with C IN placement.
C IN supplies current to the input of the circuit when the
switch is turned on. In addition to supplying high-
frequency switch current, C IN also provides a stable
voltage source for the internal MCP16321/2 circuitry.
Unstable PWM operation can result if there are
excessive transients or ringing on the V IN pin of the
MCP16321/2 device. In Figure 5-1 , C IN is placed close
to the V IN pins. A ground plane on the bottom of the
board provides a low resistive and low inductive path
for the return current. The next priority in placement is
the freewheeling current loop formed by C OUT and L
while strategically placing the C OUT return close to C IN
return. Next, C BOOST should be placed between the
boost pin and the switch node pin. This leaves space
close to the MCP16321/2 V FB pin to place R TOP and
R BOT . R TOP and R BOT are routed away from the switch
node so noise is not coupled into the high-impedance
V FB input.
Bottom layer is ground plane
V OUT
C OUT
C OUT
L
R PG 10 Ω
C BOOST
GND
MCP16321/2
R BOT R TOP
Trace on
bottom layer
V IN
C IN
C IN
GND
FIGURE 5-1:
DS22285A-page 22
Recommended Layout.
? 2011 Microchip Technology Inc.
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