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参数资料
| 型号： | MCP1640EV-SBC |
| 厂商： | Microchip Technology |
| 文件页数： | 9/32页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR MCP1640 |
| 标准包装： | 1 |
| 主要目的： | DC/DC，步升 |
| 输出及类型： | 1，非隔离 |
| 输出电压： | 2V，3.3V 或 5V |
| 电流 - 输出： | 100mA，350mA |
| 输入电压： | 0.35 ~ 5.5V |
| 稳压器拓扑结构： | 升压 |
| 频率 - 开关： | 500kHz |
| 板类型： | 完全填充 |
| 已供物品： | 板 |
| 已用 IC / 零件： | MCP1640 |
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MCP1640/B/C/D
3.0
PIN DESCRIPTIONS
TABLE 3-1:
PIN FUNCTION TABLE
Pin
Name
MCP1640/B/C/D MCP1640/B/C/D
SOT23 2x3 DFN
Description
SW
GND
EN
FB
V OUT
V IN
S GND
P GND
V OUTS
V OUTP
EP
1
2
3
4
5
6
—
—
—
—
—
5
—
4
1
—
8
2
3
7
6
9
Switch Node, Boost Inductor Input Pin
Ground Pin
Enable Control Input Pin
Feedback Voltage Pin
Output Voltage Pin
Input Voltage Pin
Signal Ground Pin
Power Ground Pin
Output Voltage Sense Pin
Output Voltage Power Pin
Exposed Thermal Pad (EP); must be connected to V SS.
3.1
Switch Node Pin (SW)
3.6
Power Supply Input Voltage Pin
Connect the inductor from the input voltage to the SW
pin. The SW pin carries inductor current and can be as
high as 800 mA peak. The integrated N-Channel switch
drain and integrated P-Channel switch source are inter-
(V IN )
Connect the input voltage source to V IN . The input
source should be decoupled to GND with a 4.7 μF
minimum capacitor.
nally connected at the SW node.
3.7
Signal Ground Pin (S GND )
3.2
Ground Pin (GND)
The signal ground pin is used as a return for the
The ground or return pin is used for circuit ground con-
nection. Length of trace from input cap return, output
cap return, and GND pin should be made as short as
integrated V REF and error amplifier. In the 2x3 DFN
package, the S GND and power ground (P GND ) pins are
connected externally.
possible to minimize noise on the GND pin. In the
3.8
Power Ground Pin (P GND )
SOT23-6 package, a single ground pin is used.
The power ground pin is used as a return for the high-
3.3
Enable Pin (EN)
current N-Channel switch. In the 2x3 DFN package, the
P GND and S GND pins are connected externally.
The EN pin is a logic-level input used to enable or
disable device switching, and lower quiescent current
while disabled. A logic high (>90% of V IN ) will enable
the regulator output. A logic low (<20% of V IN ) will
ensure that the regulator is disabled.
3.9 Output Voltage Sense Pin (V OUTS )
The output voltage sense pin connects the regulated
output voltage to the internal bias circuits. In the 2x3
DFN package, the V OUTS and output voltage power
(V OUTP ) pins are connected externally.
3.4
Feedback Voltage Pin (FB)
3.10
Output Voltage Power Pin (V OUTP )
The FB pin is used to provide output voltage regulation
by using a resistor divider. The FB voltage will be 1.21V
typical with the output voltage in regulation.
3.5 Output Voltage Pin (V OUT )
The output voltage pin connects the integrated
P-Channel MOSFET to the output capacitor. The FB
voltage divider is also connected to the V OUT pin for
voltage regulation.
? 2011 Microchip Technology Inc.
The output voltage power pin connects the output volt-
age to the switch node. High current flows through the
integrated P-Channel and out of this pin to the output
capacitor and output. In the 2x3 DFN package, V OUTP
and V OUTS are connected externally.
3.11 Exposed Thermal Pad (EP)
There is no internal electrical connection between the
Exposed Thermal Pad (EP) and the S GND and P GND
pins. They must be connected to the same potential on
the Printed Circuit Board (PCB).
DS22234B-page 9
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