参数资料
型号: MCP1725-2502E/MC
厂商: Microchip Technology
文件页数: 18/32页
文件大小: 0K
描述: IC REG LDO 2.5V .5A 8DFN
产品培训模块: High Current LDOs
标准包装: 150
稳压器拓扑结构: 正,固定式
输出电压: 2.5V
输入电压: 最高 6V
电压 - 压降(标准): 0.21V @ 500mA
稳压器数量: 1
电流 - 输出: 500mA(最小)
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 8-VFDFN 裸露焊盘
供应商设备封装: 8-DFN(2x3)
包装: 管件
产品目录页面: 665 (CN2011-ZH PDF)
MCP1725
4.6
C DELAY Input
4.7
Shutdown Input (SHDN)
The C DELAY input is used to provide the power-up delay
timing for the power good output, as discussed in the
previous section. By adding a capacitor from the
C DELAY pin to ground, the PWRGD power-up time
delay can be adjusted from 200 μs (no capacitance on
C DELAY ) to 300 ms (0.1 μF of capacitance on C DELAY ).
See Section 1.0 “Electrical Characteristics” for
C DELAY timing tolerances.
Once the power good threshold (rising) has been
reached, the C DELAY pin charges the external capacitor
to V IN . The charging current is 140 nA (typical). The
PWRGD output will transition high when the C DELAY pin
voltage has charged to 0.42V. If the output falls below
the power good threshold limit during the charging time
between 0.0V and 0.42V on the C DELAY pin, the
C DELAY pin voltage will be pulled to ground, thus reset-
ting the timer. The C DELAY pin will be held low until the
output voltage of the LDO has once again risen above
the power good rising threshold. A timing diagram
showing C DELAY , PWRGD and V OUT is shown in
The SHDN input is an active-low input signal that turns
the LDO on and off. The SHDN threshold is a
percentage of the input voltage. The typical value of
this shutdown threshold is 30% of V IN , with minimum
and maximum limits over the entire operating
temperature range of 45% and 15%, respectively.
The SHDN input will ignore low-going pulses (pulses
meant to shut down the LDO) that are up to 400 ns in
pulse width. If the shutdown input is pulled low for more
than 400 ns, the LDO will enter Shutdown mode. This
small bit of filtering helps to reject any system noise
spikes on the shutdown input signal.
On the rising edge of the SHDN input, the shutdown
circuitry has a 30 μs delay before allowing the LDO
output to turn on. This delay helps to reject any false
turn-on signals or noise on the SHDN input signal. After
the 30 μs delay, the LDO output enters its soft-start
period as it rises from 0V to its final regulation value. If
the SHDN input signal is pulled low during the 30 μs
delay period, the timer will be reset and the delay time
will start over again on the next rising edge of the
SHDN input. The total time from the SHDN input going
high (turn-on) to the LDO output being in regulation is
V OUT
V PWRGD_TH
typically 100 μs. See Figure 4-5 for a timing diagram of
the SHDN input.
T PG
C DELAY
V IN (typ)
T OR
400 ns (typ)
0V
C DELAY Threshold (0.42V)
30 μs
70 μs
SHDN
PWRGD
V OUT
FIGURE 4-4:
C DELAY and PWRGD Timing
Diagram.
DS22026B-page 18
FIGURE 4-5:
Diagram.
Shutdown Input Timing
? 2007 Microchip Technology Inc.
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MCP1725-5002E/MC 功能描述:低压差稳压器 - LDO 500mA CMOS LDO Vout=5.0V RoHS:否 制造商:Texas Instruments 最大输入电压:36 V 输出电压:1.4 V to 20.5 V 回动电压(最大值):307 mV 输出电流:1 A 负载调节:0.3 % 输出端数量: 输出类型:Fixed 最大工作温度:+ 125 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-20