参数资料
型号: MCP1790T-3302E/DB
厂商: Microchip Technology
文件页数: 13/34页
文件大小: 0K
描述: IC REG LDO 3.3V 70MA SOT-223-3
标准包装: 4,000
稳压器拓扑结构: 正,固定式
输出电压: 3.3V
输入电压: 6 V ~ 30 V
电压 - 压降(标准): 0.7V @ 70mA
稳压器数量: 1
电流 - 输出: 70mA(最小)
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: TO-261-4,TO-261AA
供应商设备封装: SOT-223-3
包装: 带卷 (TR)
其它名称: MCP1790T-3302E/DBTR
MCP1790/MCP1791
3.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1 and Table 3-2 .
TABLE 3-1:
MCP1790 PIN FUNCTION TABLE
Pin No.
SOT-223-3
1
2,Tab
3
Pin No.
DDPAK-3
1
2,Tab
3
Symbol
V IN
GND
V OUT
Unregulated Supply Voltage
Ground Terminal
Regulated Output Voltage
Function
TABLE 3-2:
MCP1791 PIN FUNCTION TABLE
Pin No.
SOT-223-5
1
2
3
4
5
Tab
Pin No.
DDPAK-5
1
2
3
4
5
Tab
Symbol
SHDN
V IN
GND
V OUT
PWRGD
N/C
Function
Shutdown Input
Unregulated Supply Voltage
Ground Terminal
Regulated Output Voltage
Power Good Open-Drain Output
Connected to Ground
No connection
3.1
Input Voltage Supply (V IN )
3.4
Shutdown (SHDN)
Connect the unregulated or regulated input voltage
source to V IN . If the input voltage source is located
several inches away from the regulator or the input
source is a battery, it is recommended that an input
capacitor is used. A typical input capacitance value of
1 μF to 10 μF should be sufficient for most applications.
The type of capacitor used can be ceramic, tantalum or
aluminum electrolytic. The low ESR characteristics of
the ceramic will yield better noise and PSRR
performance at high-frequency.
The SHDN pin is an active-low input signal that turns
the regulator output voltage on and off. When the
SHDN input is at a logic-high level, the regulator output
voltage is enabled. When the SHDN input is pulled to a
logic-low level, the regulator output voltage is disabled.
When the SHDN input is pulled low, the PWRGD output
signal also goes low and the regulator enters a low
quiescent current shutdown state where the typical qui-
escent current is 10 μA. The SHDN pin is bonded to V IN
in the 3-pin versions of the regulator. See Table 4-1 .
3.2
Ground (GND)
3.5
Power Good Output (PWRGD)
Tie GND to the negative side of the output and the
negative side of the input capacitor. Only the regulator
bias current flows out of this pin; there is no high
current. The regulator output regulation is referenced to
this pin. Minimize voltage drops between this pin and
the negative side of the load.
3.3 Regulated Output Voltage (V OUT )
The V IN pin is the regulated output voltage of the
regulator. A minimum output capacitance of 1.0 μF
tantalum, 1.0 μF electrolytic, or 4.7 μF ceramic is
required for stability. The MCP1790 is stable with
ceramic, tantalum, and electrolytic capacitors. See
Section 4.7 “Output Capacitor” for output capacitor
selection guidance.
? 2010 Microchip Technology Inc.
The PWRGD pin is an open-drain output signal that is
used to indicate when the regulator output voltage is
within 90% (typically) of its nominal regulation value.
The PWRGD threshold has a typical hysteresis value
of 2%. The typical PWRGD delay time due to V OUT
rising above 90% +3% (maximum hysteresis) is 30 μs.
The typical PWRGD delay time due to V OUT falling
below 90% is 235 μs. These delay times are internally
fixed.
3.6 Exposed Pad (EP)
The DDPAK package has an exposed tab on the
package. A heat sink may be mounted to the tab to aid
in the removal of heat from the package during
operation.
The exposed tab or pad of all of the available packages
is at the ground potential of the regulator.
DS22075B-page 13
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