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| 型号： | MCP1824ST-3002E/DB |
| 厂商： | Microchip Technology |
| 文件页数： | 19/34页 |
| 文件大小： | 0K |
| 描述： | IC REG LDO 3V .3A SOT223-3 |
| 标准包装： | 1 |
| 稳压器拓扑结构： | 正，固定式 |
| 输出电压： | 3V |
| 输入电压： | 最高 6V |
| 电压 - 压降（标准）： | 0.2V @ 300mA |
| 稳压器数量： | 1 |
| 电流 - 输出： | 300mA（最小） |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | TO-261-4，TO-261AA |
| 供应商设备封装： | SOT-223-3 |
| 包装： | 标准包装 |
| 产品目录页面： | 666 (CN2011-ZH PDF) |
| 其它名称： | MCP1824ST-3002E/DBDKR |
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MCP1824/MCP1824S
4.3
Output Capacitor
delay is fixed at 110 μs (typical). After the time delay
The MCP1824/MCP1824S requires a minimum output
capacitance of 1 μF for output voltage stability. Ceramic
capacitors are recommended because of their size,
cost, and environmental robustness qualities.
Aluminum-electrolytic and tantalum capacitors can be
used on the LDO output as well. The Equivalent Series
Resistance (ESR) of the electrolytic output capacitor
must be no greater than 1 ohm. The output capacitor
should be located as close to the LDO output as is
practical. Ceramic materials X7R and X5R have low
temperature coefficients and are well within the
acceptable ESR range required. A typical 1 μF X7R
0805 capacitor has an ESR of 50 milli-ohms.
Larger LDO output capacitors can be used with the
MCP1824/MCP1824S to improve dynamic
performance and power supply ripple rejection
performance. A maximum of 22 μF is recommended.
Aluminum-electrolytic capacitors are not recom-
mended for low temperature applications of < -25°C.
period, the PWRGD output will go high, indicating that
the output voltage is stable and within regulation limits.
If the output voltage of the LDO falls below the power
good threshold, the power good output will transition
low. The power good circuitry has a 200 μs delay when
detecting a falling output voltage, which helps to
increase noise immunity of the power good output and
avoid false triggering of the power good output during
fast output transients. See Figure 4-2 for power good
timing characteristics.
When the LDO is put into Shutdown mode using the
SHDN input, the power good output is pulled low
immediately, indicating that the output voltage will be
out of regulation. The timing diagram for the power
good output when using the shutdown input is shown in
The power good output is an open-drain output that can
be pulled up to any voltage that is equal to or less than
the LDO input voltage. This output is capable of sinking
1.2 mA minimum (V PWRGD < 0.4V maximum).
4.4
Input Capacitor
Low input source impedance is necessary for the LDO
VPWRGD_TH
output to operate properly. When operating from
batteries, or in applications with long lead length
(> 10 inches) between the input source and the LDO,
some input capacitance is recommended. A minimum
VOUT
TPG
of 1.0 μF to 4.7 μF is recommended for most
applications.
For applications that have output step load
requirements, the input capacitance of the LDO is very
important. The input capacitance provides the LDO
with a good local low-impedance source to pull the
transient currents from, in order to respond quickly to
PWRGD
VOH
TVDET_PWRGD
VOL
the output load step. For good step response
performance, the input capacitor should be of
equivalent (or higher) value than the output capacitor.
The capacitor should be placed as close to the input of
the LDO as is practical. Larger input capacitors will also
help reduce any high-frequency noise on the input and
output of the LDO and reduce the effects of any
inductance that exists between the input source
voltage and the input capacitance of the LDO.
FIGURE 4-2:
V IN
30 μs
T OR
70 μ s
Power Good Timing.
4.5
Power Good Output (PWRGD)
SHDN
T PG
The PWRGD output is used to indicate when the output
voltage of the LDO is within 92% (typical value, see
and Maximum specifications) of its nominal regulation
value.
As the output voltage of the LDO rises, the PWRGD
output will be held low until the output voltage has
exceeded the power good threshold plus the hysteresis
value. Once this threshold has been exceeded, the
V OUT
PWRGD
power good time delay is started (shown as T PG in the
Electrical Characteristics table). The power good time
2007 Microchip Technology Inc.
FIGURE 4-3:
Shutdown.
Power Good Timing from
DS22070A-page 19
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| MCP1824ST-3302E/DB | 功能描述:低压差稳压器 - LDO 300 mA CMOS LDO Vout 3.3V Ext Temp Range RoHS:否 制造商:Texas Instruments 最大输入电压:36 V 输出电压:1.4 V to 20.5 V 回动电压（最大值）:307 mV 输出电流:1 A 负载调节:0.3 % 输出端数量: 输出类型:Fixed 最大工作温度:+ 125 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-20 |
| MCP1824ST-5002E/DB | 功能描述:低压差稳压器 - LDO 300 mA CMOS LDO Vout 5.0V Ext Temp Range RoHS:否 制造商:Texas Instruments 最大输入电压:36 V 输出电压:1.4 V to 20.5 V 回动电压（最大值）:307 mV 输出电流:1 A 负载调节:0.3 % 输出端数量: 输出类型:Fixed 最大工作温度:+ 125 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-20 |
| MCP1824ST-ADJE/DB | 功能描述:低压差稳压器 - LDO 300 mA CMOS LDO Adj Vout Ext Temp Range RoHS:否 制造商:Texas Instruments 最大输入电压:36 V 输出电压:1.4 V to 20.5 V 回动电压（最大值）:307 mV 输出电流:1 A 负载调节:0.3 % 输出端数量: 输出类型:Fixed 最大工作温度:+ 125 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-20 |
| MCP1824T-0802E/DC | 功能描述:低压差稳压器 - LDO 300 mA CMOS LDO Vout 0.8V ETR RoHS:否 制造商:Texas Instruments 最大输入电压:36 V 输出电压:1.4 V to 20.5 V 回动电压（最大值）:307 mV 输出电流:1 A 负载调节:0.3 % 输出端数量: 输出类型:Fixed 最大工作温度:+ 125 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-20 |
| MCP1824T-0802E/OT | 功能描述:低压差稳压器 - LDO 300 mA CMOS LDO Vout 0.8V ETR RoHS:否 制造商:Texas Instruments 最大输入电压:36 V 输出电压:1.4 V to 20.5 V 回动电压（最大值）:307 mV 输出电流:1 A 负载调节:0.3 % 输出端数量: 输出类型:Fixed 最大工作温度:+ 125 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-20 |
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