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| 型号： | MCP18480T-I/SS |
| 厂商： | Microchip Technology |
| 文件页数： | 45/64页 |
| 文件大小： | 871K |
| 描述： | IC HOT SWAP CTRLR -48V 20SSOP |
| 标准包装： | 1,600 |
| 类型： | 热交换控制器 |
| 应用： | IP 电话，LAN 网络供电，网络路由器和交换机 |
| 内部开关： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-SSOP（0.209"，5.30mm 宽） |
| 供应商设备封装： | 20-SSOP |
| 包装： | 带卷 (TR) |
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?2003 Microchip Technology Inc.
DS20091B-page 45
MCP18480
6.8.2
OV (OVERVOLTAGE) BLOCK
The overvoltage block behaves similarly to the under-
voltage block in that it monitors an input voltage by
comparing a centertap voltage on an external voltage
divider (on the OV
TH
pin) to the V
REFIN
pin voltage.
If the centertap voltage is below the reference, the input
voltage is not excessive. If the centertap voltage is
greater than the V
NEG
+ V
REFIN
pin voltages, the sup-
ply voltage is higher than the programmed acceptable
maximum voltage limit. An internal flag is then acti-
vated to inform the MCP18480 that the input voltage
has exceeded the preset limit.
The Overvoltage Active signal deasserts when the
input voltage drops back below the threshold
determined by the external resistors (R
OV1
and R
OV2
).
EQUATION 6-4: OVERVOLTAGE VOLTAGE
CONDITION
6.8.3
FET-GOOD BLOCK
The FET-good block monitors the voltage between the
drain of the external MOSFET and on the V
NEG
pin at
power-up. It delays assertion of PWRGOOD until the
drain-to-source voltage of the external FET is accept-
ably low and the voltage at the GATE pin is about 8V.
The comparator operation is similar to Undervoltage
and Overvoltage blocks.
To prevent applying excessive voltages to the gates of
the FETs in the Undervoltage circuit, a resistive voltage
divider is employed between ground and the V
NEG
pin.
Similarly, the drain of the external MOSFET can be
exposed to voltages at around V
NEG
during normal
operation and as high as ground (typically 48V above
V
NEG
).
The FET good block also monitors the GATE pin. When
the GATE pin becomes >V
NEG
+8V and the DRAIN
TH
pin is within its programmed range, the output of the
FET good block is active.
The internal FET good signal goes high and remains
active until a fault condition (Undervoltage, Overvolt-
age or Current Limit) is detected. Any of these condi-
tions hold the PWRGOOD signal deasserted until the
fault condition is removed and the external FET gate
and drain voltages are acceptable.
V
REFIN
V
NEG
R
OV2
"
R
OV1
R
OV2
+
(
)
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