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参数资料
| 型号： | MCP2030-I/ST |
| 厂商： | Microchip Technology |
| 文件页数： | 54/66页 |
| 文件大小： | 0K |
| 描述： | IC KEYLESS ENTRY AFE 14TSSOP |
| 标准包装： | 96 |
| RF 型： | ISM |
| 频率： | 125kHz |
| 特点： | 10kbps |
| 封装/外壳： | 14-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 14-TSSOP |
| 包装： | 管件 |
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MCP2030
REGISTER 5-6:
CONFIGURATION REGISTER 5 (ADDRESS: 0101)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
AUTOCHSEL
AGCSIG
MODMIN1 MODMIN0 LCZSEN3
LCZSEN2
LCZSEN1
LCZSEN0
R5PAR
bit 8
bit 0
bit 8
bit 7
bit 6-5
bit 4-1
bit 0
AUTOCHSEL : Auto-Channel Select bit
1 = Enabled – Device selects channel(s) that has demodulator output “high” at the end of T AGC ; or otherwise,
blocks the channel(s).
0 = Disabled – Device follows channel enable/disable bits defined in Register 0
AGCSIG : Demodulator Output Enable bit, after the AGC loop is active
1 = Enabled – No output until AGC is regulating at around 20 mV PP at input pins. The AGC Active Status bit
is set when the AGC begins regulating.
0 = Disabled – The device passes signal of any level it is capable of detecting
MODMIN<1:0> : Minimum Modulation Depth bit
00 = 33%
01 = 60%
10 = 14%
11 = 8%
LCZSEN<3:0> (1) : LCZ Sensitivity Reduction bit
0000 = -0 dB (Default)
:
1111 = -30 dB
R5PAR : Register 5 Parity bit – set/cleared so the 9-bit register contains odd parity – an odd number of set bits
Legend:
Note 1:
Assured monotonic increment (or decrement) by design.
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
REGISTER 5-7:
COLUMN PARITY REGISTER 6 (ADDRESS: 0110)
R/W-0
COLPAR7
R/W-0
COLPAR6
R/W-0
COLPAR5
R/W-0
COLPAR4
R/W-0
COLPAR3
R/W-0
COLPAR2
R/W-0
COLPAR1
R/W-0
COLPAR0
R/W-0
R6PAR
bit 8
bit 0
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Legend:
COLPAR7 : Set/Cleared so that this 8th parity bit + the sum of the Config. register row parity bits contain an odd
number of set bits.
COLPAR6 : Set/Cleared such that this 7th parity bit + the sum of the 7th bits in Config. registers 0 through 5 contain
an odd number of set bits.
COLPAR5 : Set/Cleared such that this 6th parity bit + the sum of the 6th bits in Config. registers 0 through 5 contain
an odd number of set bits.
COLPAR4 : Set/Cleared such that this 5th parity bit + the sum of the 5th bits in Config. registers 0 through 5 contain
an odd number of set bits.
COLPAR3 : Set/Cleared such that this 4th parity bit + the sum of the 4th bits in Config. registers 0 through 5 contain
an odd number of set bits.
COLPAR2 : Set/Cleared such that this 3rd parity bit + the sum of the 3rd bits in Config. registers 0 through 5 contain
an odd number of set bits.
COLPAR1 : Set/Cleared such that this 2nd parity bit + the sum of the 2nd bits in Config. registers 0 through 5 contain
an odd number of set bits.
COLPAR0 : Set/Cleared such that this 1st parity bit + the sum of the 1st bits in Config. registers 0 through 5 contain
an odd number of set bits.
R6PAR : Register 6 Parity bit – set/cleared so the 9-bit register contains odd parity – an odd number of set bits
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
DS21981A-page 54
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
? 2005 Microchip Technology Inc.
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