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| 型号： | MCP2120T-I/SL |
| 厂商： | Microchip Technology |
| 文件页数： | 34/36页 |
| 文件大小： | 0K |
| 描述： | IC ENCODR/DECODR 2.5V IR 14-SOIC |
| 标准包装： | 2,600 |
| 类型： | 红外线编码器/解码器 |
| 电压 - 电源，模拟： | 2.5 V ~ 5.5 V |
| 电压 - 电源，数字： | 2.5 V ~ 5.5 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 14-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 14-SOIC |
| 包装： | 带卷 (TR) |
| 配用： | MCP212XDM-ND - BOARD DEVELOPMENT IRDA |
| 其它名称： | MCP2120TI/SL |
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2007 Microchip Technology Inc.
DS21618B-page 7
MCP2120
2.5
Modulation
When the UART receives data to be transmitted, the
data needs to be modulated. This modulated signal
drives the IR transceiver module. Figure 2-2 shows the
encoding of the modulated signal.
Each bit time is comprised of 16-bit clocks. If the value
to be transmitted (as determined by the TX pin) is a
logic low, then the TXIR pin will output a low level for
7-bit clock cycles, a logic high level for 3-bit clock
cycles, and then the remaining 6-bit clock cycles will be
low. If the value to transmit is a logic high, then the
TXIR pin will output a low level for the entire 16-bit clock
cycles.
2.6
Demodulation
The modulated signal from the IR transceiver module
needs to be demodulated to form the received data. As
demodulation occurs, the bit value is placed on the RX
pin in UART format. Figure 2-3 shows the decoding of
the modulated signal.
Each bit time is comprised of 16 bit clocks. If the value
to be received is a logic low, then the RXIR pin will be
a low level for the first 3-bit clock cycles, and then the
remaining 13-bit clock cycles will be high. If the value to
be received is a logic high, then the RXIR pin will be a
high level for the entire 16-bit clock cycles. The level on
the RX pin will be in the appropriate state for the entire
16 clock cycles.
FIGURE 2-2:
Encoding
FIGURE 2-3:
Decoding
BITCLK
TX
TXIR
01
0
1
16 CLK
Start Bit
Data bit 0
Data bit 1
Data bit 2
Data bit...
7 CLK
12 Tosc
BITCLK
RX
RXIR
01
0
1
≥ 1.6 s
13 CLK (or
≤ 50.5 s typical)
16 CLK
8 CLK
Start Bit
Data bit 0
Data bit 1
Data bit 2
Data bit ...
(CLK)
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