参数资料
型号: MCP23016-I/SP
厂商: Microchip Technology
文件页数: 17/38页
文件大小: 0K
描述: IC I/O EXPANDER I2C 16B 28SDIP
标准包装: 15
接口: I²C
输入/输出数: 16
中断输出:
频率 - 时钟: 400kHz
电源电压: 2 V ~ 5.5 V
工作温度: -40°C ~ 85°C
安装类型: 通孔
封装/外壳: 28-DIP(0.300",7.62mm)
供应商设备封装: 28-DIP
包装: 管件
包括: POR
产品目录页面: 684 (CN2011-ZH PDF)
MCP23016
DS20090C-page 24
2007 Microchip Technology Inc.
TABLE 2-5:
I2C BUS DATA REQUIREMENTS
Param
No.
Symbol
Characteristic
Min
Max
Units
Conditions
100
THIGH
Clock High Time
100 kHz mode
4.0
s
400 kHz mode
0.6
s
101
TLOW
Clock Low Time
100 kHz mode
4.7
s
400 kHz mode
1.3
s
102
TR
SDA and SCL Rise
Time
100 kHz mode
1000
ns
400 kHz mode
20 + 0.1 CB
300
ns
CB is specified to be from
10 - 400 pF
103
TF
SDA and SCL Fall
Time
100 kHz mode
300
ns
400 kHz mode
20 + 0.1 CB
300
ns
CB is specified to be from
10 - 400 pF
90
TSU:STA
START Condition
Setup Time
100 kHz mode
4.7
s
Only relevant for repeated
START condition (Note 1)
400 kHz mode
0.6
s
91
THD:STA
START Condition
Hold Time
100 kHz mode
4.0
s
After this period, the first
clock pulse is generated
400 kHz mode
0.6
s
106
THD:DAT
Data Input Hold
Time
100 kHz mode
0
ns
400 kHz mode
0
0.9
s
107
TSU:DAT
Data Input Setup
Time
100 kHz mode
250
ns
400 kHz mode
100
ns
92
TSU:STO
STOP Condition
Setup Time
100 kHz mode
4.7
s
400 kHz mode
0.6
s
109
TAA
Output Valid from
Clock
100 kHz mode
3500
ns
400 kHz mode
ns
110
TBUF
Bus Free Time
100 kHz mode
4.7
s
Time the bus must be free
before a new transmis-
sion can start (Note 1)
400 kHz mode
1.3
s
CB
Bus Capacitive Loading
400
pF
111
TWAIT
Clock wait time
after ninth pulse
100 kHz mode
12 s
s
Time the bus must remain
free after the ninth clock
pulse before a new
transmission can start.
400 kHz mode
12 s
s
Note 1:
These parameters are characterized but not tested.
2:
As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3:
A Fast mode (400 kHz) I2C bus device can be used in a Standard mode (100 kHz) I2C bus system, but the
requirement TSU:DAT
≥ 250 ns must then be met. This will automatically be the case if the device does not
stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal,
it must output the next data bit to the SDA line TR max.+TSU:DAT = 1000 + 250 = 1250 ns (according to the
Standard mode I2C bus specification), before the SCL line is released.
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