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| 型号： | MCP25020-I/P |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PDIP14 |
| 封装： | 0.300 INCH, PLASTIC, DIP-14 |
| 文件页数： | 31/66页 |
| 文件大小： | 1028K |
| 代理商： | MCP25020-I/P |
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2007 Microchip Technology Inc.
DS21664D-page 37
MCP2502X/5X
6.0
PWM MODULE
6.1
Description
There are two Pulse Width Modulation (PWM) modules
(PWM1 and PWM2) that generate up to a 10-bit
resolution output signal on GP2 and GP3, respectively.
Each of these outputs can be separately enabled, with
each having its own associated timer, duty cycle and
period registers for controlling the PWM output shape.
Each PWM module contains a set of master/slave duty
cycle registers, providing up to a 10-bit resolution PWM
output. Figure 6-1 shows a simplified block diagram of
the PWM module. A PWM output has a time base
(period) and a time that the output stays high (duty
cycle), as shown in Figure 6-2. The frequency of the
PWM is the inverse of the period (1/period).
At power-on, the PWM outputs are not enabled until
after
the
self-configuration
sequence
has
been
completed (i.e., all SRAM registers have been loaded
with their default values) to prevent invalid signals from
occurring on the PWM outputs.
FIGURE 6-1:
SIMPLIFIED BLOCK
DIAGRAM
The PWM outputs can be forced to their default POR
conditions if CAN bus communication is lost and is
enabled via OPTREG2.PDEFEN. The system designer
must implement a hand-shaking protocol, such that the
MCP2505X will receive a valid message into one of the
receive buffers before four successive scheduled
transmissions occur. If a valid message is not received,
the PWM outputs GP2 and GP3 will automatically
reconfigure to their default conditions. This includes the
PWM module itself being disabled and the GPIO being
forced low, high or tri-state.
FIGURE 6-2:
PWM OUTPUT
6.2
PWM Timer Modules
There are two 8-bit timers supporting the two PWM
outputs. Both timers have a prescaler only. The timers
are readable and writable and are cleared on any
device reset or when the timer is turned off.
The input clock (FOSC/4) has a prescale option of 1:1,
1:4 or 1:16, selected by control bits TnCKPS[1:0] in
register TnCON<5:4> (where n corresponds to the
appropriate timer).
Each timer module has an 8-bit period register, PRn.
PRn is a readable and writable register. The timer
module increments from 00h until it matches PRn and
then resets to 00h on the next increment cycle. The
PRn register is set when the device is reset.
Each timer can be shut off by clearing control bit
TMRnON (TnCON<7>).
6.2.1
TIMER MODULE PRESCALER
The prescaler counters are cleared when a write to the
TnCON or TMRn register or any device reset (RST
reset or Power-on reset) occurs.
6.3
PWM Modules
Each PWM module contains a set of master/slave duty
cycle registers, providing up to a 10-bit resolution PWM
output. Figure 6-2 shows a simplified block diagram of
the PWM module.
6.3.1
PWM PERIOD
The PWM period is specified by writing to the PRn
register. The PWM period can be calculated using the
following formula:
When TMRn is equal to PRn, the following two events
occur on the next cycle:
TMRn is cleared
The PWM duty cycle is latched from PWMnDCH
into PWMnDBH
PWMnDCH
PWMnDBH
TMRn
Prn
Note
Comparator
DDR<Y>
GP<Y>
(PWMn)
Comparator
TnCON
(2 LSB)
Duty cycle
R
S
Q
1
registers
Note 1: 8-bit timer is concatenated with 2-bit internal
Q clock or 2 bits of the prescaler to create
10-bit time base
TMRn = PRn
Period
Duty Cycle
TMRn = PRn
TMRn=Duty Cycle
PWM period
PR
n
() 1
+
[]*4T
OS C
* TMRn prescale value
()
=
PWM frequency
1
PWM period
()
=
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