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参数资料
型号： MCP25050T-I/SL
元件分类： 微控制器/微处理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PDSO14
封装： 0.150 INCH, PLASTIC, SOIC-14
文件页数： 19/64页
文件大小： 1232K
代理商： MCP25050T-I/SL
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TABLE 4-3:
COMMAND MESSAGES (EXTENDED IDENTIFIER)
Information Request Messages (to MCP2502X/5X)
Standard ID
Extended ID
Data Bytes
1
0
987 654321 0R
T
R
I
D
E
DLC
1
7
1
6
RXBEID8
(8 bits)
RXBEID0
(8 bits)
Read A/D Regs
xxxx xxxxxx x 11 1 0 0 0 8* x x
xxxx xxxx
xxxx *000
n/a
Read Control Regs xxxx xxxxxx x 11 0 1 1 1 7* x x
xxxx xxxx
xxxx *001
n/a
Read Config Regs
xxxx xxxxxx x 11 0 1 0 1 5* x x
xxxx xxxx
xxxx *010
n/a
Read CAN Error
xxxx xxxxxx x 11 0 0 1 1 3* x x
xxxx xxxx
xxxx *011
n/a
Read PWM Config
xxxx xxxxxx x 11 0 1 1 0 6* x x
xxxx xxxx
xxxx *100
n/a
Read User Mem
xxxx xxxxxx x 11 1 0 0 0 8* x x
xxxx xxxx
xxxx *101
n/a
Read User Mem
xxxx xxxxxx x 11 1 0 0 0 8* x x
xxxx xxxx
xxxx *110
n/a
Read Register
xxxx xxxxxx x 1 1 0 0 0 0 1* x x
addr
xxxx *111
n/a
Output Messages (from MCP2502X/5X)
Standard ID
Extended ID
Data Bytes
1
0
987 65 432 1 0 R
T
R
I
D
E
DLC
1
7
1
6
RXBEID8
(8 bits)
RXBEID0
(8 bits)
Read A/D Regs
x xxx xx xxx x x 01 1 0 0 0 8 x x xxxx xxxx
xxxx *000
IOINTFL
GPIO
AN0H
AN1H
AN10L
AN2H
AN3H
AN32L
Read Control Regs
x xxx xx xxx x x 01 0 1 1 1 7 x x xxxx xxxx
xxxx *001
ADCON0 ADCON1 OPTREG OPTREG
STCON
IOINTEN
IOINTPO
n/a
Read Config Regs
x xxx xx xxx x x 01 0 1 0 1 5 x x xxxx xxxx
xxxx *010
DDR
GPIO
CNF1
CNF2
CNF3
n/a
Read CAN Error
x xxx xx xxx x x 01 0 0 1 1 3 x x xxxx xxxx
xxxx *011
EFLG
TEC
REC
n/a
Read PWM Config
x xxx xx xxx x x 01 0 1 1 0 6 x x xxxx xxxx
xxxx *100
PR1
PR2
T1CON
T2CON
PWM1D
PWM2D
n/a
Read User Mem
x xxx xx xxx x x 01 1 0 0 0 8 x x xxxx xxxx
xxxx *101 USERID0 USERID1 USERID2 USERID3 USERID4 USERID5 USERID6 USERID7
Read User Mem
x xxx xx xxx x x 01 1 0 0 0 8 x x xxxx xxxx
xxxx *110 USERID8 USERID9 USERID1 USERID1 USERID1 USERID1 USERID1 USERID1
Read Register
x xxx xx xxx x x 0 1 0 0 0 0 1x x
addr
xxxx *111
value
n/a
Input Messages (to MCP2502X/5X)
Standard ID
Extended ID
Data Bytes
1
0
987 65 432 1 0 R
T
R
I
D
E
DLC
1
7
1
6
RXBEID8
(8 bits)
RXBEID0
(8 bits)
Write Register
x xxx xx xxx x x 0 1 0 0 1 1 3 x x xxxx xxxx
xxxx x000
addr
mask
value
n/a
Write TX Message
x xxx xx xxx x x 0 1 0 1 0 0 4 x x xxxx xxxx
xxxx x001 TX0SIDH TX0SIDL
TX0EID8
TX0EID0
n/a
Write TX Message
x xxx xx xxx x x 0 1 0 1 0 0 4 x x xxxx xxxx
xxxx x010 TX1SIDH TX1SIDL
TX1EID8
TX1EID0
n/a
Write TX Message
x xxx xx xxx x x 0 1 0 1 0 0 4 x x xxxx xxxx
xxxx x011 TX2SIDH TX2SIDL
TX2EID8
TX2EID0
n/a
Write I/O Configura- x xxx xx xxx x x 0 1 0 1 0 1 5 x x xxxx xxxx
xxxx x100
IOINTEN
IOINTPO
DDR
OPTREG ADCON1
n/a
Write RX Mask
x xxx xx xxx x x 0 1 0 1 0 0 4 x x xxxx xxxx
xxxx x101
RXM-
RXMSIDL RXMEID8 RXMEID0
n/a
Write RX Filter0
x xxx xx xxx x x 0 1 0 1 0 0 4 x x xxxx xxxx
xxxx x110 RXF0SID RXF0SID RXF0EID RXF0EID
n/a
Write RX Filter1
x xxx xx xxx x x 0 1 0 1 0 0 4 x x xxxx xxxx
xxxx x111
RXF1SID RXF1SID RXF1EID RXF1EID
n/a
* If using non-RTR messages for information request messages (IRM), the RTR bit = 0, DLC bit field = 0, and bit 3 of the IRM ID = 1. Also, bit 3 of the output message ID = 0.
If using RTR messages for IRMs, the RTR bit = 1, DLC bit field = number of bytes in corresponding output message, and bit three of the IRM ID = x (don’t care), also, bit 3 of the
output message = x (don’t care).
** User-defined IRM IDs must be different from input message IDs to avoid message contention between the corresponding output message and the input message.
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