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| 型号： | MCP3021A6T-E/OT |
| 厂商： | Microchip Technology |
| 文件页数： | 5/26页 |
| 文件大小： | 0K |
| 描述： | ADC 10BIT I2C INTERFACE SOT23-5 |
| 标准包装： | 1 |
| 位数： | 10 |
| 采样率（每秒）： | 22.3k |
| 数据接口： | I²C，串行 |
| 转换器数目： | 1 |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | SC-74A，SOT-753 |
| 供应商设备封装： | SOT-23-5 |
| 包装： | 标准包装 |
| 输入数目和类型： | 1 个单端，单极 |
| 其它名称： | MCP3021A6T-E/OTDKR |
2003 Microchip Technology Inc.
DS21805A-page 13
MCP3021
4.0
DEVICE OPERATION
The MCP3021 employs a classic SAR architecture.
This architecture uses an internal sample and hold
capacitor to store the analog input while the conversion
is taking place. At the end of the acquisition time, the
input switch of the converter opens and the device uses
the collected charge on the internal sample and hold
capacitor to produce a serial 10-bit digital output code.
The acquisition time and conversion is self-timed using
an internal clock. After each conversion, the results are
stored in a 10-bit register that can be read at any time.
Communication with the device is accomplished with a
2-wire I2C interface. Maximum sample rates of
22.3 ksps are possible with the MCP3021 in a continu-
ous conversion mode and an SCL clock rate of
400 kHz.
4.1
Digital Output Code
The digital output code produced by the MCP3021 is a
function of the input signal and power supply voltage
(VDD). As the VDD level is reduced, the LSB size is
reduced accordingly. The theoretical LSB size is shown
below.
EQUATION
The output code of the MCP3021 is transmitted serially
with MSB first, the format of the code being straight
binary.
4.2
Conversion Time (tCONV)
The conversion time is the time required to obtain the
digital result once the analog input is disconnected
from the holding capacitor. With the MCP3021, the
specified conversion time is typically 8.96 s. This time
is dependent on the internal oscillator and independent
of SCL.
4.3
Acquisition Time (tACQ)
The acquisition time is the amount of time the sample
cap array is acquiring charge.
The acquisition time is, typically, 1.12 s. This time is
dependent on the internal oscillator and independent of
SCL.
4.4
Sample Rate
Sample rate is the inverse of the maximum amount of
time that is required from the point of acquisition of the
first conversion to the point of acquisition of the second
conversion.
The sample rate can be measured either by single or
continuous conversions. A single conversion includes
a Start Bit, Address Byte, Two Data Bytes and a Stop
bit. This sample rate is measured from one Start Bit to
the next Start Bit.
For continuous conversions (requested by the Master
by issuing an acknowledge after a conversion), the
maximum sample rate is measured from conversion to
conversion, or a total of 18 clocks (two data bytes and
two Acknowledge bits). Refer to Section 5-2, “Device
Addressing”.
FIGURE 4-1:
Transfer Function.
LSB SIZE
VDD
1024
------------
=
VDD = Supply voltage
AIN
00 0000 0001
(1)
00 0000 0011
(3)
11 1111 1110
(1022)
Output Code
VDD-1.5 LSB
.5 LSB
1.5 LSB
VDD-2.5 LSB
2.5 LSB
00 0000 0000
(0)
00 0000 0010
(2)
11 1111 1111
(1023)
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