参数资料
型号: MCP3201T-BI/SN
厂商: Microchip Technology
文件页数: 34/40页
文件大小: 0K
描述: IC ADC 12BIT 2.7V 1CH SPI 8-SOIC
标准包装: 3,300
位数: 12
采样率(每秒): 100k
数据接口: 串行,SPI?
转换器数目: 1
电压电源: 单电源
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOICN
包装: 带卷 (TR)
输入数目和类型: 1 个单端,单极
MCP3201
DS21290F-page 4
1998-2011 Microchip Technology Inc.
TEMPERATURE CHARACTERISTICS
High Level Output Voltage
VOH
4.1
V
IOH = -1 mA, VDD = 4.5V
Low Level Output Voltage
VOL
——
0.4
V
IOL = 1 mA, VDD = 4.5V
Input Leakage Current
ILI
-10
10
A
VIN = VSS or VDD
Output Leakage Current
ILO
-10
10
A
VOUT = VSS or VDD
Pin Capacitance
(all inputs/outputs)
CIN, COUT
10
pF
VDD = 5.0V (Note 1)
TA = +25°C, f = 1 MHz
Timing Parameters:
Clock Frequency
fCLK
1.6
0.8
MHz
VDD = 5V (Note 3)
VDD = 2.7V (Note 3)
Clock High Time
tHI
312
ns
Clock Low Time
tLO
312
ns
CS Fall To First Rising CLK Edge
tSUCS
100
ns
CLK Fall To Output Data Valid
tDO
200
ns
See Test Circuits, Figure 1-2
CLK Fall To Output Enable
tEN
200
ns
See Test Circuits, Figure 1-2
CS Rise To Output Disable
tDIS
100
ns
See Test Circuits, Figure 1-2
CS Disable Time
tCSH
625
ns
D
OUT Rise Time
tR
100
ns
See Test Circuits, Figure 1-2
D
OUT Fall Time
tF
100
ns
See Test Circuits, Figure 1-2
Power Requirements:
Operating Voltage
VDD
2.7
5.5
V
Operating Current
IDD
300
210
400
A
VDD = 5.0V, DOUT unloaded
VDD = 2.7V, DOUT unloaded
Standby Current
IDDS
—0.5
2
A
CS = VDD = 5.0V
Electrical Specifications:
Unless otherwise indicated, VDD = +2.7V to +5.5V, VSS = GND.
Parameters
Sym
Min
Typ
Max
Units
Conditions
Temperature Ranges
Specified Temperature Range
TA
-40
+85
°C
Operating Temperature Range
TA
-40
+85
°C
Storage Temperature Range
TA
-65
+150
°C
Thermal Package Resistances
Thermal Resistance, 8L-MSOP
JA
—211
°C/W
Thermal Resistance, 8L-PDIP
JA
—89.5
°C/W
Thermal Resistance, 8L-SOIC
JA
149.5
°C/W
Thermal Resistance, 8L-TSSOP
JA
—139
°C/W
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications:
All parameters apply at VDD = 5V, VSS = 0V, VREF = 5V, TA = -40°C to +85°C, fSAMPLE = 100 ksps, and
fCLK = 16*fSAMPLE, unless otherwise noted.
Parameter
Sym
Min
Typ
Max
Units
Conditions
Note 1:
This parameter is established by characterization and not 100% tested.
2:
See graph that relates linearity performance to VREF level.
3:
Because the sample cap will eventually lose charge, effective clock rates below 10 kHz can affect linearity performance,
especially at elevated temperatures. See Section 6.2 “Maintaining Minimum Clock Speed” for more information.
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