参数资料
型号: MCP3421A2T-E/CH
厂商: Microchip Technology
文件页数: 17/42页
文件大小: 0K
描述: IC ADC 18BIT 3.75SPS 1CH SOT23-6
产品培训模块: MCP3901 Analog Front End
标准包装: 1
位数: 18
采样率(每秒): 3.75
数据接口: I²C,串行
转换器数目: 1
电压电源: 单电源
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: SOT-23-6
供应商设备封装: SOT-23-6
包装: 标准包装
输入数目和类型: 2 个单端,双极;1 个差分,单极
产品目录页面: 672 (CN2011-ZH PDF)
其它名称: MCP3421A2T-E/CHDKR
MCP3421
DS22003E-page 24
2009 Microchip Technology Inc.
TABLE 5-4:
I2C SERIAL TIMING SPECIFICATIONS
Electrical Specifications: Unless otherwise specified, all limits are specified for T
A = -40 to +85°C,
VIN+ = VIN- = VREF/2, VSS = 0V, VDD = +2.7V to +5.0V.
Parameters
Sym
Min
Typ
Max
Units
Conditions
Standard Mode (100 kHz)
Clock frequency
fSCL
100
kHz
Clock high time
THIGH
4000
ns
Clock low time
TLOW
4700
ns
SDA and SCL rise time
TR
1000
ns
From VIL to VIH (Note 1)
SDA and SCL fall time
TF
300
ns
From VIH to VIL (Note 1)
START condition hold time
THD:STA
4000
ns
START (Repeated) condition
setup time
TSU:STA
4700
ns
Data hold time
THD:DAT
0
3450
ns
Data input setup time
TSU:DAT
250
ns
STOP condition setup time
TSU:STO
4000
ns
Output valid from clock
TAA
0
3750
ns
Bus free time
TBUF
4700
ns
Time between START and
STOP conditions.
Fast Mode (400 kHz)
Clock frequency
TSCL
400
kHz
Clock high time
THIGH
600
ns
Clock low time
TLOW
1300
ns
SDA and SCL rise time
TR
20 + 0.1Cb
300
ns
From VIL to VIH (Note 1)
SDA and SCL fall time
TF
20 + 0.1Cb
300
ns
From VIH to VIL (Note 1)
START condition hold time
THD:STA
600
ns
START (Repeated) condition
setup time
TSU:STA
600
ns
Data hold time
THD:DAT
0
900
ns
Data input setup time
TSU:DAT
100
ns
STOP condition setup time
TSU:STO
600
ns
Output valid from clock
TAA
0
1200
ns
Bus free time
TBUF
1300
ns
Time between START and
STOP conditions.
Note 1: This parameter is ensured by characterization and not 100% tested.
2: This specification is not a part of the I2C specification. This specification is equivalent to the Data Hold
Time (THD:DAT) plus SDA Fall (or rise) time: TAA = THD:DAT + TF (OR TR).
3: If this parameter is too short, it can create an unintended Start or Stop condition to other devices on the
bus line. If this parameter is too long, Clock Low time (TLOW) can be affected.
4: For Data Input: This parameter must be longer than t
SP. If this parameter is too long, the Data Input Setup
(TSU:DAT) or Clock Low time (TLOW) can be affected.
For Data Output: This parameter is characterized, and tested indirectly by testing TAA parameter.
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