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| 型号： | MCP3422EV |
| 厂商： | Microchip Technology |
| 文件页数： | 20/58页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL MCP3422 PICKIT SERIAL |
| 产品培训模块： | MCP3901 Analog Front End |
| 标准包装： | 1 |
| 系列： | PICkit™ |
| ADC 的数量： | 2 |
| 位数： | 18 |
| 采样率（每秒）： | 3.75 |
| 数据接口： | 串行 |
| 输入范围： | ±2.048 V |
| 工作温度： | -40°C ~ 125°C |
| 已用 IC / 零件： | MCP3422 |
| 已供物品： | 板 |
| 产品目录页面： | 672 (CN2011-ZH PDF) |
| 相关产品： | MCP3422A0T-E/SNTR-ND - IC ADC 18BIT 3.75SPS 2CH 8-SOIC MCP3422A0T-E/MSTR-ND - IC ADC 18BIT 3.75SPS 2CH 8-MSOP MCP3422A0T-E/MCTR-ND - IC ADC 18BIT 3.75SPS 2CH 8-DFN MCP3422A0-E/SN-ND - IC ADC 18BIT3.75SPS 2CH 8-SOIC MCP3422A0-E/MS-ND - IC ADC 18BIT 3.75SPS 2CH 8-MSOP MCP3422A0-E/MC-ND - IC ADC 18BIT 3.75SPS 2CH 8-DFN |
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2009 Microchip Technology Inc.
DS22088C-page 27
MCP3422/3/4
TABLE 5-4:
I2C SERIAL TIMING SPECIFICATIONS
Electrical Specifications: Unless otherwise specified, all limits are specified for TA = -40 to +85°C, VDD = +2.7V to +5.0V,
VSS = 0V, CHn+ = CHn- = VREF/2.
Parameters
Sym
Min
Typ
Max
Units
Conditions
Standard Mode (100 kHz)
Clock frequency
fSCL
0
—
100
kHz
Clock high time
THIGH
4000
—
ns
Clock low time
TLOW
4700
—
ns
SDA and SCL rise time
TR
—
1000
ns
SDA and SCL fall time
TF
—
300
ns
START condition hold time
THD:STA
4000
—
ns
After this period, the first clock
pulse is generated.
START (Repeated) condition
setup time
TSU:STA
4700
—
ns
Data hold time
THD:DAT
0
—
3450
ns
Data input setup time
TSU:DAT
250
—
ns
STOP condition setup time
TSU:STO
4000
—
ns
Output valid from clock
TAA
0
—
3750
ns
Bus free time
TBUF
4700
—
ns
Time between START and STOP
conditions.
Fast Mode (400 kHz)
Clock frequency
TSCL
0
—
400
kHz
Clock high time
THIGH
600
—
ns
Clock low time
TLOW
1300
—
ns
SDA and SCL rise time
TR
20 + 0.1Cb
—
300
ns
SDA and SCL fall time
TF
20 + 0.1Cb
—
300
ns
START condition hold time
THD:STA
600
—
ns
After this period, the first clock
pulse is generated
START (Repeated) condition
setup time
TSU:STA
600
—
ns
Data hold time
THD:DAT
0
—
900
ns
Data input setup time
TSU:DAT
100
—
ns
STOP condition setup time
TSU:STO
600
—
ns
Output valid from clock
TAA
0
—
1200
ns
Bus free time
TBUF
1300
—
ns
Time between START and STOP
conditions.
Note
1:
This parameter is ensured by characterization and not 100% tested.
2:
This specification is not a part of the I2C specification. This specification is equivalent to the Data Hold Time (THD:DAT)
plus SDA Fall (or rise) time: TAA = THD:DAT + TF (OR TR).
3:
If this parameter is too short, it can create an unintended Start or Stop condition to other devices on the bus line. If this
parameter is too long, Clock Low time (TLOW) can be affected.
4:
For Data Input: If this parameter is too long, the Data Input Setup (TSU:DAT) or Clock Low time (TLOW) can be affected.
For Data Output: This parameter is characterized, and tested indirectly by testing TAA parameter.
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