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| 型号： | MCP3550-50E/MS |
| 厂商： | Microchip Technology |
| 文件页数： | 16/36页 |
| 文件大小： | 0K |
| 描述： | IC ADC 22BIT 2.7V 1CH 8MSOP |
| 产品培训模块： | MCP3901 Analog Front End |
| 标准包装： | 100 |
| 位数： | 22 |
| 采样率（每秒）： | 12.5 |
| 数据接口： | 串行，SPI? |
| 转换器数目： | 1 |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-TSSOP，8-MSOP（0.118"，3.00mm 宽） |
| 供应商设备封装： | 8-MSOP |
| 包装： | 管件 |
| 输入数目和类型： | 1 个差分，单极 |
| 产品目录页面： | 672 (CN2011-ZH PDF) |
| 配用： | MCP355XDV-MS1-ND - BOARD DEV SENSOR APP MCP355X MCP355XDM-TAS-ND - BOARD DEMO TINY APP SNSR MCP355X |
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2009 Microchip Technology Inc.
DS21950E-page 23
MCP3550/1/3
5.3
Single Conversion Mode
If a rising edge of Chip Select (CS) occurs during tCONV,
a subsequent conversion will not take place and the
device will enter low-power Shutdown mode after
tCONV completes. This is referred to as Single
Conversion mode. This operation is demonstrated in
Figure 5-2. Note that a falling edge of CS during the
same conversion that detected a rising edge, as in
Figure 5-2, will not initiate a new conversion. The data
must be read during sleep mode, with CSN low, and will
be lost as soon as the part enters in shutdown mode
(with a rising edge of CSN). After the final data bit has
been clocked out on the 25th clock, the SDO/RDY pin
will go active-high.
5.3.1
READY FUNCTION OF SDO/RDY
PIN, SINGLE CONVERSION MODE
At every falling edge of CS during the internal
conversion, the state of the internal conversion is
latched on the SDO/RDY pin to give ready or busy
information. A High state means the device is currently
performing an internal conversion and data cannot be
clocked out. A Low state means the device has finished
its conversion and the data is ready for retrieval on the
falling edge of SCK. This operation is demonstrated in
Figure 5-4. Note that the device has been put into
Single Conversion mode with the first rising edge of
CS.
FIGURE 5-4:
RDY Functionality in Single
Conversion Mode.
5.4
Continuous Conversion Mode
If no rising edge of CS occurs during any given
conversion per Figure 5-3, a subsequent conversion
will take place and the contents of the previous conver-
sion will be overwritten. This operation is demonstrated
in Figure 5-5. Once conversion output data has started
to be clocked out, the output buffer is not refreshed until
all 24 bits have been clocked. A complete read must
occur in order to read the next conversion in this mode.
The subsequent conversion data to be read will then be
the most recent conversion. The conversion time is
fixed and cannot be shortened by the rising edge of CS.
This rising edge will place the part in Shutdown mode
and all conversion data will be lost.
The transfer of data from the SINC filter to the output
buffer is demonstrated in Figure 5-5. If the previous
conversion data is not clocked out of the device, it will
be lost and replaced by the new conversion. When the
device is in Continuous Conversion mode, the most
recent conversion data is always present at the output
register for data retrieval.
FIGURE 5-5:
Most Current Continuous
Conversion Mode Data.
If a conversion is in process, it cannot be terminated
with the rising edge of CS. SDO/RDY must first
transition to a Low state, which will indicate the end of
conversion.
Note:
The Ready state is latched on each falling
edge of CS and will not dynamically
update if CS is held low. CS must be
toggled high through low.
tCONV
CS
Int. Osc
SDO/RDY
Hi-Z
tCONV
CS
Int. Osc
SCK & SDO/RDY
A
B
C
Conversion B data is clocked
out of the device here.
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