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| 型号： | MCP3905A-I/SS |
| 厂商： | Microchip Technology |
| 文件页数： | 14/32页 |
| 文件大小： | 0K |
| 描述： | IC POWER METERING-1 PHASE 24SSOP |
| 产品培训模块： | MCP3901 Analog Front End |
| 标准包装： | 59 |
| 输入阻抗： | 390 千欧 |
| 测量误差： | 0.1% |
| 电压 - 高输入/输出： | 2.4V |
| 电压 - 低输入/输出： | 0.85V |
| 电流 - 电源： | 2.7mA |
| 电源电压： | 4.5 V ~ 5.5 V |
| 测量仪表类型： | 单相 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-SSOP（0.209"，5.30mm 宽） |
| 供应商设备封装： | 24-SSOP |
| 包装： | 管件 |
| 产品目录页面： | 677 (CN2011-ZH PDF) |
| 配用： | MCP3905RD-PM1-ND - REFERENCE DESIGN FOR MCP3905 MCP3905EV-ND - BOARD DEMO FOR MCP3905 |
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MCP3905A/05L/06A
3.5
Voltage Channel (CH1-,CH1+)
3.11
Oscillator (OSC1, OSC2)
CH1- and CH1+ are the fully differential analog voltage
input channels for voltage measurement. The linear
and specified region of these channels have a
maximum differential voltage of ±660 mV and a
maximum absolute voltage of ±1V, with respect to
A GND . Up to ±6V can be applied to these pins without
the risk of permanent damage.
Refer to Section 1.0 “Electrical Characteristics” .
OSC1 and OSC2 provide the master clock for the
device. A resonant crystal or clock source with a similar
sinusoidal waveform must be placed across these pins
to ensure proper operation. The typical clock frequency
specified is 3.579545 MHz. However, the clock
frequency can be with the range of 1 MHz to 4 MHz
without disturbing measurement error. Appropriate
load capacitance should be connected to these pins for
proper operation.
3.6
Master Clear (MCLR)
A full-swing, single-ended clock source may be
connected to OSC1 with proper resistors in series to
MCLR controls the reset for both delta-sigma ADCs, all
digital registers, the SINC filters for each channel and
ensure no ringing of the clock source due to fast
transient edges.
all accumulators post multiplier. A logic ‘ 0 ’ resets all
registers and holds both ADCs in a Reset condition.
The charge stored in both ADCs is flushed and their
3.12
Negative Power Output Logic Pin
(NEG)
output is maintained to 0x0000h. The only block
consuming power on the digital power supply during
Reset is the oscillator circuit.
NEG detects the phase difference between the two
channels and will go to a logic ‘ 1 ’ state when the phase
difference is greater than 90° (i.e., when the measured
real power is negative). The output state is synchro-
3.7
Reference (REFIN/OUT)
nous with the rising-edge of HF OUT and maintains the
REFIN/OUT is the output for the internal 2.4V
reference. This reference has a typical temperature
logic ‘ 1 ’ until the real power becomes positive again
and HF OUT shows a pulse.
coefficient of 15 ppm/°C and a tolerance of ±2%. In
3.13
Ground Connection (D GND )
addition, an external reference can also be used by
applying voltage to this pin within the specified range.
This pin requires appropriate bypass capacitors to
A GND , even when using the internal reference only.
Refer to Section 5.0 “Applications Information” .
D GND is the ground connection to internal digital
circuitry (SINC filters, multiplier, HPF, LPF, digital-to-
frequency converter and oscillator). To ensure
accuracy and noise cancellation, D GND must be
connected to the same ground as A GND , preferably
3.8
Analog Ground (A GND )
with a star connection. If a digital ground plane is
available, it is recommended that this device be tied to
A GND is the ground connection to internal analog
circuitry (ADCs, PGA, band gap reference, POR). To
ensure accuracy and noise cancellation, this pin must
be connected to the same ground as D GND , preferably
with a star connection. If an analog ground plane is
available, it is recommended that this device be tied to
this plane of the PCB. This plane should also reference
all other analog circuitry in the system.
this plane of the Printed Circuit Board (PCB). This
plane should also reference all other digital circuitry in
the system.
3.14 High-Frequency Output (HF OUT )
HF OUT is the high-frequency output of the device and
supplies the instantaneous real-power information. The
output is a periodic pulse output, with its period
proportional to the measured real power, and to the
3.9
Frequency Control Logic Pins
HF C constant defined by F0, F1 and F2 pin logic states.
This output is the preferred output for calibration due to
(F2, F1, F0)
F2, F1 and F0 select the high-frequency output and
low-frequency output pin ranges by changing the
value of the constants F C and H FC used in the device
transfer function. F C and H FC are the frequency
constants that define the period of the output pulses
for the device.
faster output frequencies, giving smaller calibration
times. Since this output gives instantaneous real
power, the 2 ω ripple on the output should be noted.
However, the average period will show minimal drift.
3.15 Frequency Output (F OUT0 , F OUT1 )
F OUT0 and F OUT1 are the frequency outputs of the
device that supply the average real-power information.
3.10
Gain Control Logic Pins (G1, G0)
The outputs are periodic pulse outputs, with its period
proportional to the measured real power, and to the F c
G1 and G0 select the PGA gain on Channel 0 from
three different values: 1, 8 and 16.
DS22011B-page 14
constant, defined by F0 and F1 pin logic states. These
pins include high-output drive capability for direct use
of electromechanical counters and 2-phase stepper
motors. Since this output supplies average real power,
any 2 ω ripple on the output pulse period is minimal.
? 2006-2011 Microchip Technology Inc.
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