参数资料
型号: MCP3905EV
厂商: Microchip Technology
文件页数: 12/30页
文件大小: 0K
描述: BOARD DEMO FOR MCP3905
产品培训模块: MCP3901 Analog Front End
标准包装: 1
主要目的: 电源管理,电度表/功率表
嵌入式:
已用 IC / 零件: MCP3905/6
主要属性: 1 相 120/220 VAC 板载无变压器 AC/DC 5V 电源
已供物品: 板,CD
产品目录页面: 677 (CN2011-ZH PDF)
相关产品: MCP3905L-I/SS-ND - IC POWER METERING-1 PHASE 24SSOP
MCP3905LT-I/SSTR-ND - IC POWER METERING-1 PHASE 24SSOP
MCP3906AT-I/SS-ND - IC POWER METERING-1 PHASE 24SSOP
MCP3905AT-I/SS-ND - IC POWER METERING-1 PHASE 24SSOP
MCP3906A-I/SS-ND - IC POWER METERING-1 PHASE 24SSOP
MCP3905A-I/SS-ND - IC POWER METERING-1 PHASE 24SSOP
MCP3905/06
3.4
Current Channel (CH0-, CH0+)
3.9
Frequency Control Logic Pins
CH0- and CH0+ are the fully differential analog voltage
input channels for the current measurement, containing
a PGA for small-signal input, such as shunt current-
sensing. The linear and specified region of this channel
is dependant on the PGA gain. This corresponds to a
maximum differential voltage of ±470 mV/GAIN and
maximum absolute voltage, with respect to A GND , of
(F2, F1, F0)
F2, F1 and F0 select the high-frequency output and
low-frequency output pin ranges by changing the value
of the constants F C and H FC used in the device transfer
function. F C and H FC are the frequency constants that
define the period of the output pulses for the device.
±1V. Up to ±6V can be applied to these pins without the
risk of permanent damage.
3.10
Gain Control Logic Pins (G1, G0)
G1 and G0 select the PGA gain on Channel 0 from
three different values: 1, 8 and 16.
3.5
Voltage Channel (CH1-,CH1+)
3.11
Oscillator (OSC1, OSC2)
CH1- and CH1+ are the fully differential analog voltage
input channels for the voltage measurement. The linear
and specified region of these channels have a
maximum differential voltage of ±660 mV and a
maximum absolute voltage of ±1V, with respect to
A GND . Up to ±6V can be applied to these pins without
the risk of permanent damage.
OSC1 and OSC2 provide the master clock for the
device. A resonant crystal or clock source with a similar
sinusoidal waveform must be placed across these pins
to ensure proper operation. The typical clock frequency
specified is 3.579545 MHz. However, the clock
frequency can be with the range of 1 MHz to 4 MHz
without disturbing measurement error. Appropriate
load capacitance should be connected to these pins for
proper operation.
3.6
Master Clear (MCLR)
A full-swing, single-ended clock source may be
MCLR controls the reset for both delta-sigma ADCs, all
digital registers, the SINC filters for each channel and
all accumulators post multiplier. A logic ‘ 0 ’ resets all
registers and holds both ADCs in a Reset condition.
connected to OSC1 with proper resistors in series to
ensure no ringing of the clock source due to fast
transient edges.
The charge stored in both ADCs is flushed and their
3.12
Negative Power Output Logic Pin
output is maintained to 0x0000h. The only block
consuming power on the digital power supply during
Reset is the oscillator circuit.
(NEG)
NEG detects the phase difference between the two
channels and will go to a logic ‘ 1 ’ state when the phase
3.7
Reference (REFIN/OUT)
difference is greater than 90° (i.e., when the measured
active (real) power is negative). The output state is
REFIN/OUT is the output for the internal 2.4V
reference. This reference has a typical temperature
coefficient of 15 ppm/°C and a tolerance of ±2%. In
addition, an external reference can also be used by
synchronous with the rising-edge of HF OUT and
maintains the logic ‘ 1 ’ until the active (real) power
becomes positive again and HF OUT shows a pulse.
applying voltage to this pin within the specified range.
REFIN/OUT requires appropriate bypass capacitors to
3.13
Ground Connection (D GND )
A GND , even when using the internal reference only.
D GND is the ground connection to the internal digital
circuitry (SINC filters, multiplier, HPF, LPF, Digital-to-
Frequency (DTF) converter and oscillator). To ensure
3.8
Analog Ground (A GND )
accuracy and noise cancellation, D GND must be
connected to the same ground as A GND , preferably
A GND is the ground connection to the internal analog
circuitry (ADCs, PGA, band gap reference, POR). To
ensure accuracy and noise cancellation, this pin must
be connected to the same ground as D GND , preferably
with a star connection. If an analog ground plane is
available, it is recommended that this device be tied to
this plane of the Printed Circuit Board (PCB). This
plane should also reference all other analog circuitry in
the system.
DS21948E-page 12
with a star connection. If a digital ground plane is
available, it is recommended that this device be tied to
this plane of the PCB. This plane should also reference
all other digital circuitry in the system.
? 2009 Microchip Technology Inc.
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