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| 型号： | MCP3905L-I/SS |
| 厂商： | Microchip Technology |
| 文件页数： | 17/30页 |
| 文件大小： | 0K |
| 描述： | IC POWER METERING-1 PHASE 24SSOP |
| 产品培训模块： | MCP3901 Analog Front End |
| 标准包装： | 59 |
| 输入阻抗： | 390 千欧 |
| 测量误差： | 0.1% |
| 电压 - 高输入/输出： | 2.4V |
| 电压 - 低输入/输出： | 0.85V |
| 电流 - 电源： | 2.7mA |
| 电源电压： | 4.5 V ~ 5.5 V |
| 测量仪表类型： | 单相 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-SSOP（0.209"，5.30mm 宽） |
| 供应商设备封装： | 24-SSOP |
| 包装： | 管件 |
| 产品目录页面： | 677 (CN2011-ZH PDF) |
| 配用： | MCP3905RD-PM1-ND - REFERENCE DESIGN FOR MCP3905 MCP3905EV-ND - BOARD DEMO FOR MCP3905 |
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MCP3905/06
If an external voltage reference source is connected to
4.5
High-Pass Filters and Multiplier
the REFIN/OUT pin, the external voltage will be used
as the reference for both current and voltage channel
ADCs. The voltage across the source resistor will then
be the difference between the internal and external
voltage. The allowed input range for the external
voltage source goes from 2.2V to 2.6V for accurate
measurement error. A V REF value outside of this range
will cause additional heating and power consumption
due to the source resistor, which might affect
measurement error.
The active (real) power value is extracted from the DC
instantaneous power. Therefore, any DC offset
component present on Channel 0 and Channel 1
affects the DC component of the instantaneous power
and will cause the real-power calculation to be
erroneous. In order to remove DC offset components
from the instantaneous power signal, a high-pass filter
has been introduced on each channel. Since the
high-pass filtering introduces phase delay, identical
high-pass filters are implemented on both channels.
4.4
Power-On Reset (POR)
The filters are clocked by the same digital signal,
ensuring a phase difference between the two channels
The MCP3905/06 contains an internal POR circuit that
monitors analog supply voltage AV DD during operation.
This circuit ensures correct device startup at system
power-up/power-down events. The POR circuit has
built-in hysteresis and a timer to give a high degree of
immunity to potential ripple and noise on the power
supplies, allowing proper settling of the power supply
during power-up. A 0.1 μF decoupling capacitor should
be mounted as close as possible to the AV DD pin,
providing additional transient immunity (see
The threshold voltage is typically set at 4V, with a
tolerance of about ±5%. If the supply voltage falls below
this threshold, the MCP3905/06 will be held in a Reset
condition (equivalent to applying logic ‘ 0 ’ on the MCLR
pin). The typical hysteresis value is approximately
200 mV in order to prevent glitches on the power
supply.
of less than one MCLK period. Under typical conditions
(MCLK = 3.58 MHz), this phase difference is less than
0.005°, with a line frequency of 50 Hz. The cut-off
frequency of the filter (4.45 Hz) has been chosen to
induce minimal gain error at typical line frequencies,
allowing sufficient settling time for the desired
applications. The two high-pass filters can be disabled
by applying a logic ‘ 0 ’ to the HPF pin.
0
-5
-10
-15
-20
-25
-30
-35
Once a power-up event has occurred, an internal timer
prevents the part from outputting any pulse for
-40
0.1
1
10
100
1000
approximately 1s (with MCLK = 3.58 MHz), thereby
preventing potential metastability due to intermittent
resets caused by an unsettled regulated power supply.
power-up and a power-down event in the typical
conditions.
AV DD
5V
4.2V
4V
1s
Frequency (Hz)
FIGURE 4-4: HPF Magnitude Response
(MCLK = 3.58 MHz).
The multiplier output gives the product of the two high-
pass-filtered channels, corresponding to instantaneous
active (real) power. Multiplying two sine wave signals
by the same ω frequency gives a DC component and a
2 ω component. The instantaneous power signal
contains the active (real) power of its DC component,
while also containing 2 ω components coming from the
line frequency multiplication. These 2 ω components
come for the line frequency (and its harmonics) and
must be removed in order to extract the real-power
information. This is accomplished using the low-pass
filter and DTF converter.
0V
DEVICE
MODE
RESET
NO
PULSE
OUT
PROPER
OPERATION
RESET
Time
FIGURE 4-3:
Power-on Reset Operation.
? 2009 Microchip Technology Inc.
DS21948E-page 17
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