参数资料
型号: MCP4011T-202E/MS
厂商: Microchip Technology
文件页数: 38/54页
文件大小: 0K
描述: IC DGTL POT 2.1K 1CH 8MSOP
标准包装: 2,500
接片: 64
电阻(欧姆): 2.1k
电路数: 1
温度系数: 标准值 150 ppm/°C
存储器类型: 易失
接口: 2 线串行(芯片选择,增/减)
电源电压: 1.8 V ~ 5.5 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 8-TSSOP,8-MSOP(0.118",3.00mm 宽)
供应商设备封装: 8-MSOP
包装: 带卷 (TR)
2006 Microchip Technology Inc.
DS21978C-page 43
MCP4011/2/3/4
7.0
DESIGN CONSIDERATIONS
In the design of a system with the MCP401X devices,
the following considerations should be taken into
account:
The Power Supply
The Layout
7.1
Power Supply Considerations
The typical application will require a bypass capacitor
in order to filter high-frequency noise, which can be
induced onto the power supply's traces. The bypass
capacitor helps to minimize the effect of these noise
sources on signal integrity. Figure 7-1 illustrates an
appropriate bypass strategy.
In this example, the recommended bypass capacitor
value is 0.1 F. This capacitor should be placed as
close (within 4 mm) to the device power pin (VDD) as
possible.
The power source supplying these devices should be
as clean as possible. If the application circuit has
separate digital and analog power supplies, VDD and
VSS should reside on the analog plane.
FIGURE 7-1:
Typical Microcontroller
Connections.
7.2
Layout Considerations
Inductively-coupled AC transients and digital switching
noise can degrade the input and output signal integrity,
potentially masking the MCP4011/2/3/4’s performance.
Careful board layout will minimize these effects and
increase the Signal-to-Noise Ratio (SNR). Bench
testing has shown that a multi-layer board utilizing a
low-inductance ground plane, isolated inputs, isolated
outputs and proper decoupling are critical to achieving
the performance that the silicon is capable of providing.
Particularly harsh environments may require shielding
of critical signals.
If low noise is desired, breadboards and wire-wrapped
boards are not recommended.
VDD
VSS
M
C
P4
01
1/
2/
3/
4
0.1 F
PIC
Mi
cr
oco
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tr
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r
0.1 F
U/D
CS
W
B
A
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