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| 型号： | MCP40D19T-103E/LT |
| 厂商： | Microchip Technology |
| 文件页数： | 31/43页 |
| 文件大小： | 0K |
| 描述： | IC DGTL POT 10K 128TAPS SC70-5 |
| 标准包装： | 1 |
| 接片： | 128 |
| 电阻（欧姆）： | 10k |
| 电路数： | 1 |
| 温度系数： | 标准值 150 ppm/°C |
| 存储器类型： | 易失 |
| 接口： | I²C |
| 电源电压： | 1.8 V ~ 5.5 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 6-TSSOP（5 引线），SC-88A，SOT-353 |
| 供应商设备封装： | SC-70-5 |
| 包装： | 标准包装 |
| 产品目录页面： | 674 (CN2011-ZH PDF) |
| 其它名称： | MCP40D19T-103E/LTDKR |
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2009 Microchip Technology Inc.
DS22152B-page 37
MCP40D17/18/19
5.3
Software Reset Sequence
At times it may become necessary to perform a
Software Reset Sequence to ensure the MCP40D17/
18/19 device is in a correct and known I2C Interface
state. This only resets the I2C state machine.
This is useful if the MCP40D17/18/19 device powers up
in an incorrect state (due to excessive bus noise, etc),
or if the Master Device is reset during communication.
Figure 5-11 shows the communication sequence to
software reset the device.
FIGURE 5-11:
Software Reset Sequence
Format.
The 1st Start bit will cause the device to reset from a
state in which it is expecting to receive data from the
Master Device. In this mode, the device is monitoring
the data bus in Receive mode and can detect the Start
bit forces an internal Reset.
The nine bits of ‘1’ are used to force a Reset of those
devices that could not be reset by the previous Start bit.
This occurs only if the MCP40D17/18/19 is driving an A
on the I2C bus, or is in output mode (from a Read
command) and is driving a data bit of ‘0’ onto the I2C
bus. In both of these cases, the previous Start bit could
not be generated due to the MCP40D17/18/19 holding
the bus low. By sending out nine ‘1’ bits, it is ensured
that the device will see a A (the Master Device does not
drive the I2C bus low to acknowledge the data sent by
the
MCP40D17/18/19),
which
also
forces
the
MCP40D17/18/19 to reset.
The 2nd Start bit is sent to address the rare possibility
of an erroneous write. This could occur if the Master
Device was reset while sending a Write command to
the MCP40D17/18/19, AND then as the Master Device
returns to normal operation and issues a Start condition
while the MCP40D17/18/19 is issuing an A. In this case
if the 2nd Start bit is not sent (and the Stop bit was sent)
the MCP40D17/18/19 could initiate a write cycle.
The Stop bit terminates the current I2C bus activity.
The MCP40D17/18/19 wait to detect the next Start
condition.
This sequence does not effect any other I2C devices
which may be on the bus, as they should disregard this
as an invalid command.
5.4
Serial Commands
The
MCP40D17/18/19
devices
support
2
serial
commands. These commands are:
The I2C command formats have been defined so to
support the SMBus version 2.0 Write Byte/Word
Protocol
formats
and
Read
Byte/Word
Protocol
formats.
The
SMBus
specification
defines
this
operation is Section 5 of the Version 2.0 document
(August 3, 2000).
This protocol format may be convienient for customers
using library routines for the I2C bus, where all they
need to do is specify the command (read, write, ...) with
the Device Address, the Register Address, and the
Data.
If higher data throughput is desired, please look at the
MCP4017/18/19 devices which have a simplier I2C
command format.
Note:
This technique should be supported by
any I2C compliant device. The 24XXXX
I2C Serial EEPROM devices support this
technique,
which
is
documented
in
AN1028.
Note:
The potential for this erroneous write
ONLY occurs if the Master Device is reset
while sending a Write command to the
MCP40D17/18/19.
S
‘1’
S
P
Start
bit
Nine bits of ‘1’
Start bit
Stop bit
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