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| 型号： | MCP41050-I/P |
| 厂商： | Microchip Technology |
| 文件页数： | 15/28页 |
| 文件大小： | 0K |
| 描述： | IC POT DIGITAL 50K 1CH SPI 8-DIP |
| 标准包装： | 60 |
| 接片： | 256 |
| 电阻（欧姆）： | 50k |
| 电路数： | 1 |
| 温度系数： | 标准值 800 ppm/°C |
| 存储器类型： | 易失 |
| 接口： | 3 线串行（芯片选择） |
| 电源电压： | 2.7 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 通孔 |
| 封装/外壳： | 8-DIP（0.300"，7.62mm） |
| 供应商设备封装： | 8-PDIP |
| 包装： | 管件 |
| 产品目录页面： | 676 (CN2011-ZH PDF) |
| 其它名称： | MCP41050-I/PR MCP41050-I/PR-ND |
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MCP41XXX/42XXX
DS11195C-page 22
2003 Microchip Technology Inc.
5.8
Using the MCP41XXX/42XXX in
SPI Mode 1,1
It is possible to operate the devices in SPI modes 0,0
and 1,1. The only difference between these two modes
is that, when using mode 1,1, the clock idles in the high
state, while in mode 0,0, the clock idles in the low state.
In both modes, data is clocked into the devices on the
rising edge of SCK and data is clocked out the SO pin
once the falling edge of SCK. Operations using mode
0,0 are shown in Figure 5-1. The example in
Figure 5-5 shows mode 1,1.
FIGURE 5-5:
Timing Diagram for SPI Mode 1,1 Operation.
SO
SI
SCK
CS
23
456
7
8
9
10
1
New Register Data
D7
D6
D5
D4
D3
D2
D1
D0
P1* P0
11
12
13
14
15
16
X
C1
C0
X
Channel
Select
Bits
Data Registers are
loaded on rising
edge of CS. Shift
First 16 bits Shifted out will always be zeros
Don’t
Care
Bits
Command
Bits
Don’t
Care
Bits
There must always be multiples of 16 clocks while CS is low or commands will abort.
The serial data out pin (SO) is only available on the MCP42XXX device.
COMMAND BYTE
DATA BYTE
X
register is loaded
with zeros at this time.
Data is always latched in
on the rising edge of SCK.
Data is always clocked out the SO
pin after the falling edge of SCK.
SO pin will always
drive low when CS
goes high.
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| MCP41050-ISN | 制造商:MICROCHIP 制造商全称:Microchip Technology 功能描述:Single/Dual Digital Potentiometer with SPIa?￠ Interface |
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