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| 型号： | MCP4726A2T-E/CH |
| 厂商： | Microchip Technology |
| 文件页数： | 42/86页 |
| 文件大小： | 0K |
| 描述： | IC DAC 12BIT NV EEP I2C SOT-23-6 |
| 标准包装： | 3,000 |
| 设置时间： | 6µs |
| 位数： | 12 |
| 数据接口： | EEPROM，I²C，串行 |
| 转换器数目： | 1 |
| 电压电源： | 单电源 |
| 功率耗散（最大）： | 452mW |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | SOT-23-6 |
| 供应商设备封装： | SOT-23-6 |
| 包装： | 带卷 (TR) |
| 输出数目和类型： | 1 电压，单极 |
| 采样率（每秒）： | * |
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2011-2012 Microchip Technology Inc.
DS22272C-page 47
MCP4706/4716/4726
5.3.6
HS MODE
The I2C specification requires that a High-Speed mode
device must be ‘activated’ to operate in High-Speed
(3.4 Mbit/s) mode. This is done by the master sending
a special address byte following the Start bit. This byte
is referred to as the High-Speed Master Mode Code
(HSMMC).
The MCP47X6 device does not acknowledge this byte.
However, upon receiving this command, the device
switches
to
HS
mode.
The
device
can
now
communicate at up to 3.4 Mbit/s on SDA and SCL
lines. The device will switch out of the HS mode on the
next Stop condition.
The master code is sent as follows:
1.
Start condition (S)
2.
High-Speed Master Mode Code (0000 1XXX),
The XXX bits are unique to the High-Speed (HS)
mode master.
3.
No Acknowledge (A)
After switching to the High-Speed mode, the next
transferred byte is the I2C control byte, which specifies
the device to communicate with, and any number of
data bytes plus acknowledgements. The master device
can then either issue a Repeated Start bit to address a
different device (at High-Speed) or a Stop bit to return
to Fast/Standard bus speed. After the Stop bit, any
other master device (in a multi-master system) can
arbitrate for the I2C bus.
See Figure 5-10 for illustration of HS mode command
sequence.
For more information on the HS mode, or other I2C
modes, please refer to the NXP I2C specification.
5.3.6.1
Slope Control
The slope control on the SDA output is different
between the Fast/Standard Speed and the High-Speed
clock modes of the interface.
5.3.6.2
Pulse Gobbler
The pulse gobbler on the SCL pin is automatically
adjusted to suppress spikes < 10 ns during HS mode.
FIGURE 5-10:
HS Mode Sequence.
S
A
‘0 0 0 0 1 X X X’b
Sr
A
‘Slave Address’
A/A
“Data”
P
S = Start bit
Sr = Repeated Start bit
A = Acknowledge bit
A = Not Acknowledge bit
R/W = Read/Write bit
R/W
P = Stop bit (Stop condition terminates HS mode)
F/S-mode
HS mode
HS mode continues
F/S mode
Sr
A
‘Slave Address’ R/W
HS Select Byte
Control Byte
Command/Data Byte(s)
Control Byte
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