参数资料
| 型号： | MCP7940N-I/SN |
| 厂商： | Microchip Technology |
| 文件页数： | 14/14页 |
| 文件大小： | 0K |
| 描述： | IC RTCC 64B SRAM GP 8-SOIC |
| 标准包装： | 100 |
| 类型： | 时钟/日历 |
| 特点： | 警报器，闰年，方波输出，SRAM |
| 存储容量： | 64B |
| 时间格式： | HH:MM:SS（12/24 小时） |
| 数据格式： | YY-MM-DD-dd |
| 接口： | I²C，2 线串口 |
| 电源电压： | 1.8 V ~ 5.5 V |
| 电压 - 电源，电池： | 1.3 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOICN |
| 包装： | 管件 |
2011 Microchip Technology Inc.
DS25010C-page 9
MCP7940N
FIGURE 4-2:
ACKNOWLEDGE TIMING
4.1.2
DEVICE ADDRESSING AND OPERATION
A control byte is the first byte received following the
Start condition from the master device (Figure 4-2).
The control byte for accessing the SRAM and RTCC
registers are set to ‘1101111’. The RTCC registers and
the SRAM share the same address space.
The last bit of the control byte defines the operation to
be performed. When set to a ‘1’ a read operation is
selected, and when set to a ‘0’ a write operation is
selected. The next byte received defines the address of
the data byte (Figure 4-3). The upper address bits are
transferred first, followed by the Least Significant bits
(LSb).
Following the Start condition, the MCP7940N monitors
the SDA bus, checking the device type identifier being
transmitted. Upon receiving an ‘1101111’ code, the
slave device outputs an Acknowledge signal on the
SDA line. Depending on the state of the R/W bit, the
MCP7940N will select a read or write operation.
FIGURE 4-3:
ADDRESS SEQUENCE BIT ASSIGNMENTS
SCL
9
8
7
6
5
4
3
2
11
2
3
Transmitter must release the SDA line at this point
allowing the Receiver to pull the SDA line low to
acknowledge the previous eight bits of data.
Receiver must release the SDA line at this point
so the Transmitter can continue sending data.
Data from transmitter
SDA
Acknowledge
Bit
1
101
R/W
X
A
0
SRAM RTCC CONTROL BYTE
ADDRESS BYTE
CONTROL
CODE
111
X = Don’t Care
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