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参数资料
型号： MCP79412-I/ST
元件分类： 时钟/数据恢复及定时提取
英文描述： REAL TIME CLOCK, PDSO8
封装： 4.40 MM BODY, ROHS COMPLAINT, PLASTIC, TSSOP-8
文件页数： 34/40页
文件大小： 584K
代理商： MCP79412-I/ST
MCP7941X
DS22266C-page 4
2010-2011 Microchip Technology Inc.
TABLE 1-2:
AC CHARACTERISTICS
Electrical Characteristics:
Industrial (I):
VCC = +1.8V to 5.5V
TA = -40°C to +85°C
Param.
No.
Symbol
Characteristic
Min.
Max.
Units
Conditions
1FCLK
Clock frequency
—
100
400
kHz
1.8V
VCC < 2.5V
2.5V
VCC 5.5V
2THIGH
Clock high time
4000
600
—
ns
1.8V
VCC < 2.5V
2.5V
VCC 5.5V
3TLOW
Clock low time
4700
1300
—
ns
1.8V
VCC < 2.5V
2.5V
VCC 5.5V
4TR
SDA and SCL rise time
(Note 1)
—
1000
300
ns
1.8V
VCC < 2.5V
2.5V
VCC 5.5V
5TF
SDA and SCL fall time
(Note 1)
—
1000
300
ns
1.8V
VCC < 2.5V
2.5V
VCC 5.5V
6THD:STA
Start condition hold time
4000
600
—
ns
1.8V
VCC < 2.5V
2.5V
VCC 5.5V
7TSU:STA
Start condition setup time
4700
600
—
ns
1.8V
VCC < 2.5V
2.5V
VCC 5.5V
8THD:DAT Data input hold time
0
—
ns
(Note 4)
9TSU:DAT
Data input setup time
250
100
—
ns
1.8V
VCC < 2.5V
2.5V
VCC 5.5V
10
TSU:STO
Stop condition setup time
4000
600
—
ns
1.8V
VCC < 2.5V
2.5V
VCC 5.5V
11
TAA
Output valid from clock
—
3500
900
ns
1.8V
VCC < 2.5V
2.5V
VCC 5.5V
12
TBUF
Bus free time: Time the bus
must be free before a new
transmission can start
4700
1300
—
ns
1.8V
VCC < 2.5V
2.5V
VCC 5.5V
13
TSP
Input filter spike suppression
(SDA and SCL pins)
—50
ns
(Note 1 and Note 2)
14
TWC
Write cycle time (byte or
page)
—5
ms
—
15
—
Endurance
1M
—
cycles
25°C, VCC = 5.5V Page mode
(Note 3)
Note 1: Not 100% tested.
2: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs, which provide improved
noise spike suppression. This eliminates the need for a TI specification for standard operation.
3: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance Model which can be obtained from Microchip’s web site
at www.microchip.com.
4: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300ns) of the falling edge of the SCL to avoid unintended generation of start or stop conditions.
相关PDF资料
PDF描述
MCP79411T-I/ST REAL TIME CLOCK, PDSO8
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