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| 型号： | MCP79412T-I/SN |
| 厂商： | Microchip Technology |
| 文件页数： | 10/14页 |
| 文件大小： | 0K |
| 描述： | IC RTCC 64BIT SRAM I2C 8SOIC |
| 标准包装： | 3,300 |
| 类型： | 时钟/日历 |
| 特点： | 警报器，闰年，方波输出，SRAM，唯一 ID |
| 存储容量： | 64B |
| 时间格式： | HH:MM:SS（12/24 小时） |
| 数据格式： | YY-MM-DD-dd |
| 接口： | I²C，2 线串口 |
| 电源电压： | 1.8 V ~ 5.5 V |
| 电压 - 电源，电池： | 1.3 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOICN |
| 包装： | 带卷 (TR) |
SY87702L
5
Micrel, Inc.
M9999-072706
hbwhelp@micrel.com or (408) 955-1690
FUNCTIONAL DESCRIPTION
Clock Recovery
Clock Recovery, as shown in the block diagram,
generates a clock that is at the same frequency as the
incoming data bit rate at the Serial Data input. The clock is
phase aligned by a PLL so that it samples the data in the
center of the data eye pattern.
The phase relationship between the edge transitions of
the data and those of the generated clock are compared by
a phase/frequency detector. Output pulses from the detector
indicate the required direction of phase correction. These
pulses are smoothed by an integral loop filter. The output of
the loop filter controls the frequency of the Voltage Controlled
Oscillator (VCO), which generates the recovered clock.
Frequency stability, without incoming data, is guaranteed
by an alternate reference input (REFCLK) that the PLL locks
onto when data is lost. If the Frequency of the incoming
signal varies by greater than approximately 1000ppm with
respect to the synthesizer frequency, the PLL will be declared
out of lock, and the PLL will lock to the multiplied frequency
of the reference clock.
The loop filter transfer function is optimized to enable the
PLL to track the jitter, yet tolerate the minimum transition
density expected in a received SONET data signal. This
transfer function yields a 30s data stream of continuous
1's or 0's for random incoming NRZ data.
The total loop dynamics of the clock recovery PLL
provides jitter tolerance which is better than the specified
tolerance in GR-253-CORE.
PIN NAMES
INPUTS
RDIN
± [Serial Data Input] – Differential PECL
This differential input accepts the receive serial data
stream. An internal receive PLL recovers the embedded
clock (RCLK) and data (RDOUT) information. The incoming
data rate can be within one of ten frequency ranges, or can
be one of five specific frequencies, depending on the state
of the FREQSEL and VCOSEL pins. The RDIN– pin has an
internal 75K resistor tied to VCC.
REFCLK
± [Reference Clock] – Differential PECL
This input is used as the reference for the internal
frequency synthesizer and the “training” frequency for the
receiver PLL to keep it centered in the absence of data
coming in on the RDIN input. The input frequency to
REFCLK is limited to 325MHz or less, depending on the
setting on the DIVSEL signals. The REFCLK– pin has an
internal 75K resistor tied to VCC.
CD [Carrier Detect] – PECL Input
This input controls the recovery function of the Receive
PLL and can be driven by the carrier detect output of optical
modules or from external transition detection circuitry. When
this input is HIGH, the input data stream (RDIN) is recovered
normally by the Receive PLL. When this input is LOW, the
data on the RDIN input will be internally forced to a constant
LOW, the data output RDOUT will remain LOW, the Link
Fault Indicator output LFIN forced LOW, and the clock
recovery PLL forced to lock onto the clock frequency
generated from REFCLK.
VCOSEL1, VCOSEL2 [VCO Select] – TTL Inputs
These inputs select the VCO frequency range via either
one of three wide-band PLLs, or a SONET/SDH specific
narrow-band PLL. Only the selected PLL is enabled. All
other PLL’s are disabled. Please refer to Table 1.
VCOSEL1
VCOSEL2
Choice
00
SONET/SDH
01
1.8 to 2.5GHz
10
1.25 to 1.8GHz
11
0.650 to 1.30GHz
Table. 1
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