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| 型号： | MCZ33099CEG |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 15/18页 |
| 文件大小： | 0K |
| 描述： | IC VREG ALTERNATOR ADAPT 16-SOIC |
| 标准包装： | 47 |
| 应用： | 自动 |
| 电流 - 电源： | 6.5mA |
| 电源电压： | 7 V ~ 18 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 16-SOIC W |
| 包装： | 管件 |
TYPICAL APPLICATIONS
circuitry to limit the lamp drive and regulates the lamp current
to current I dsc . When the power dissipation of the lamp driver
causes the temperature of the lamp driver to exceed a
thermal shut-down temperature limit (T Lim ), a temperature
sensing diode (D tl ) causes the thermal limit circuitry to send
a signal to the lamp driver circuitry to limit the lamp drive
current and reduce the power dissipation and resulting
device temperature. When the lamp driver is ON, but the
Lamp Drain pin voltage is not below the BAT pin voltage V bat
by at least a lamp drain short circuit threshold voltage (V Tdsc )
or ([V bat - V drain ] < V Tdsc ), comparator C ds will output a lamp
short circuit signal to the Drain Polling circuit to indicate a
lamp shorted condition. The Drain Polling circuit provides a
low duty cycle polling output to the input of the AND2 GATE
to poll the lamp driver ON, continuously testing for a lamp
short without damaging the lamp driver. The polling duty
cycle is 1.56%, (or about a 158 μ s ON pulse) at a frequency
of f msb /4, or 98.6 Hz. After the lamp short has been removed,
the comparator C ds outputs a lamp not-shorted signal to the
Drain Polling circuitry, which provides a logic [1] to the AND2
GATE, which then operates normally.
Lamp polling is also present when the lamp is ON. In this
case, lamp polling turns OFF the lamp for a short period of
time with the lamp being ON for the remainder of the time. In
this case the lamp ON duty cycle is 98.44% (or OFF for
158 μ s) at a frequency of f msb /4, or 98.6 Hz. This causes the
lamp voltage on the lamp drain pin to be greater than ignition
threshold voltage V Tign for at least 158 μ s of a 10.1 ms
period. During the lamp ON mode, the Ignition Turn Off Delay
of the Ignition Delay circuit is greater then the 10.1 ms period.
As a result, the regulator biasing remains ON even when the
IGN pin is coupled to the LAMP DRAIN pin and the lamp
drain voltage is less than voltage V Tig n most of the time when
the lamp is ON.
The lamp driver is also protected from load dump, since
during load dump, the LD signal is a logic [0], preventing the
AND2 GATE from activating the lamp driver. In addition, a
drain-to-GATE clamp device Z2 limits the drain-to-GATE
clamping voltage (V dg ) to about 40 V typically.
UNDERVOLTAGE, OVERVOLTAGE, AND LOAD
DUMP PROTECTION
protect the regulator and associated external devices. As
previously discussed, a load dump signal during load dump
will prevent GATE drive to the external MOSFET and prevent
GATE drive to the lamp driver. Thus the external and internal
MOSFETs will turn OFF during a system load dump. As
previously discussed, the undervoltage and overvoltage
signals are also provided for fault indications.
The undervoltage signal is provided on the UV line by an
undervoltage comparator C uv having a voltage reference of
1.25 V and a resistor divider voltage transfer of 1.26 from the
FB output to comparator C uv input. When voltage V fb on the
FB output becomes less than 1.52 V, the voltage at input to
comparator C uv becomes less than 1.25 V, causing
comparator C uv to output an undervoltage UV signal.
Because voltage V fb is ideally voltage V rs (or voltage V ls ),
and the ratio of V r / V rs (or V l / V ls ) is 7.45, the UV signal will
occur when the system voltage at the Remote input (or Local
input) is less than an undervoltage threshold voltage (V Tuv ),
or 11.35 V. However, GATE AND1 ensures that frequency
f ph must be greater than f 2 before an undervoltage Fault is
indicated by the lamp.
The load dump and overvoltage detection also utilizes
similar resistor dividers and voltage comparators in an
Overvoltage Detect circuitry where all comparators are
referenced to voltage V ref , or about 2.0 V. When voltage V fb
on the FB output is greater than 2.58 V, or 1.29 V ref (V fb / V ref
= 1.29), an output load dump signal of a logic [0] is generated
on the LD line. Thus during load dump, voltage V rs (or V local )
will be about 2.58 V, and the actual load dump threshold
voltage (V Tld ) will be about 19.25 V, or 1.3 V set . When
voltage V fb on the FB output is greater than 1.117 V ref (V fb /
V ref = 1.117), an output overvoltage signal is generated on
the OV line. Thus voltage V rs (or V l ) will be about 2.235 V,
and the actual overvoltage threshold voltage (V Tov ) will be
about 16.65 V, or 1.125 V set .
The regulator also indicates an overvoltage condition on
the system during the Remote fault condition when the
remote wire resistance increases to a finite value and the
system voltage is being regulated by secondary regulation at
V set2 . When a load dump occurs during secondary
regulation, the load dump threshold increases to 1.3 V set2 , or
about 24 V.
An undervoltage, overvoltage and load dump condition is
sensed by the regulator to generate fault indications and to
33099
Analog Integrated Circuit Device Data
Freescale Semiconductor
15
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