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| 型号： | MCZ33811EG |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 8/18页 |
| 文件大小： | 0K |
| 描述： | IC SOLENOID MON 5-CH 16-SOIC |
| 标准包装： | 47 |
| 应用： | 螺線管监控器 |
| 电流 - 电源： | 1mA |
| 电源电压： | 7 V ~ 17 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 16-SOIC W |
| 包装： | 管件 |
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics
Characteristics noted under conditions 10.5V ≤ V PWR ≤ 15.5V, - 40 ° C ≤ T A ≤ 125 ° C, GND = 0V, unless otherwise noted. Typical
values noted reflect the approximate parameter means at T A = 25°C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
SPI DIGITAL INTERFACE TIMING (10)
Required High State Duration on RESET for Reset to occur (11)
t RESET
1.0
–
–
μ s
Falling Edge of CS to Rising Edge of SCLK
Required Setup Time
t LEAD
100
–
–
ns
Falling Edge of SCLK to Rising Edge of CS
Required Setup Time
t LAG
0
50
ns
SI to Rising Edge of SCLK
Required Setup Time
t SI (SU)
16
–
–
ns
Rising Edge of SCLK to SI
Required Hold Time
SI, CS , SCLK Signal Rise Time (12)
SI, CS , SCLK Signal Fall Time (12)
Time from Falling Edge of CS to SO Low-impedance (13)
Time from Rising Edge of CS to SO High-impedance (14)
Time from Falling Edge of SCLK to SO Data Valid (15)
Sequential Transfer Rate
t SI (HOLD)
t R (SI)
t F (SI)
t SO (EN)
t SO (DIS)
t VALID
t STR
20
–
–
–
–
–
–
5.0
5.0
65
–
65
–
–
–
80
55
90
1.0
ns
ns
ns
ns
ns
ns
μs
Time required between data transfers
Input Capacitance (SI, SCLK)
Load Capacitance (SO)
Tri-state Output Capacitance (SO)
C INPUT
C LOAD
C TRI-STATE
7
15
200
20
pF
pF
pF
WAVEFORM DETECTION TIMINGS
Start of Activation Filter Time (16)
Detection Window Time
Sample Time
t BEGIN
t WINDOW
t SAM
200
40
400
53
72
600
66
μs
ms
μs
Notes:
10.
11.
12.
13.
14.
15.
16.
These parameters are guaranteed by design. Production test equipment uses 3.2MHz, 5.0V SPI interface.
This parameter is guaranteed by design, however it is not production tested.
Rise and Fall time of incoming SI, CS , and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
Time required for valid output status data to be available on SO pin.
Time required for output states data to be terminated at SO pin.
Time required to obtain valid data out from SO following the fall of SCLK with 200pF load.
9 μs guard band included in maximum limit
33811
Analog Integrated Circuit Device Data
8
Freescale Semiconductor
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