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参数资料
| 型号： | MF0045M-03ATxx |
| 厂商： | Mitsubishi Electric Corporation |
| 英文描述： | ER 26C 26#16 PIN RECP |
| 中文描述： | null8/16-bit数据总线闪存阿拉木图PC卡 |
| 文件页数： | 16/29页 |
| 文件大小： | 841K |
| 代理商： | MF0045M-03ATXX |
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MITSUBISHI STORAGE CARD
ATA PC CARDS
MITSUBISHI
ELECTRIC
16
1997.Nov. Rev. 1.2
HS3-0
LBA27-24
HS3-0 of the head number in CHS addressing or LBA27-
24 of the Logical Block Number in LBA addressing.
Status and Alternate Status Registers
The Status register and the Alternate Status register return
the card status when read by the host. Reading the Status
register clears a pending interrupt request while reading the
Alternate Status register does not. The Status register and
the Alternate Status register are read only registers.
D7
BSY
D6
D5
DWF
D4
DSC
D3
DRQ
D2
D1
IDX
D0
ERR
DRDY
CORR
Field
BSY
function
This bit is set when the card internal operation is
executing. When this bit is set to “1”, other bits in this
register are invalid.
DRDY indicates whether the card is capable of
performing card operations.
This bit, if set, indicates a write fault has occurred.
This bit is set when the drive seek complete.
This bit is set when the information can be transferred
between the host and Data register.
This bit is set when a correctable data error has been
occurred and the data has been corrected.
This bit is always set to “0”.
This bit is set when the previous command has ended in
some type of error. The error information is set in the
other Status register bits or Error register. This bit is
cleared by the next command.
DRDY
DWF
DSC
DRQ
CORR
IDX
ERR
Command Register
The Command register contains the command code being
sent to the device. Command execution begins immediately
after this register is written. The Command register is a
write only register.
D7
D6
D5
D4
Command
D3
D2
D1
D0
Device Control Register
This register is used to control the card interrupt request
and to issue a soft reset to the card. The Device Control
register is a write only register.
D7
X
D6
X
D5
X
D4
X
D3
1
D2
D1
nIEN
D0
0
SRST
Field
X
1
SRST
function
don’t care.
This bit is set to “1”.
This bit is set to “1” in order to force the card to perform a
Command Block Reset operation. This does not change the
Card Configuration registers as a Hardware Reset does.
The card remains in Reset until this bit is reset to “0”.
This bit is used for enabling IREQ#. When this bit is set to
“0”, IREQ# is enabled. When this bit is set to “1”, IREQ# is
disabled.
This bit is set to “0”.
nIEN
0
Drive Address Register
This register is provided for compatibility with the AT disk
drive interface.
D7
X
D6
D5
D4
D3
D2
D1
nDS1
D0
nDS0
nWTG
nHS3-0
Field
X
nWTG
function
This bit is unknown.
This bit is set to “0” when a Flash write operation is in
progress, otherwise it is set to “1”.
These bits is the negative value of Head Select bits in
Drive/Head register.
This bit is set to “0” when Slave drive is active and
selected.
This bit is set to “0” when Master drive is active and
selected.
nHS3-0
nDS1
nDS0
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