参数资料
型号: MF0064M-04AAxx
厂商: Mitsubishi Electric Corporation
英文描述: GT 10C 10#16 PIN PLUG
中文描述: 16位产品数据总线CF卡
文件页数: 16/31页
文件大小: 217K
代理商: MF0064M-04AAXX
MITSUBISHI STORAGE CARD
MF0XXXX-04BAXX series
CompactFlash CARDS
Jun.2000
. Rev. 1.1
MITSUBISHI
ELECTRIC
16/31
Drive/Head Register
The Drive/Head register is used to specify the selected
drive of a pair of drives sharing a set of registers.
D7
X
D6
LBA
D5
X
D4
DRV
D3
HS3
LBA27
D2
HS2
LBA26
D1
HS1
LBA25
D0
HS0
LBA24
Field
X
LBA
function
Undefined .
0
or
1
.
This bit is
0
for CHS addressing and
1
for Logical
Block addressing.
This bit is number of the drive which the host has
selected. When DRV is cleared, Drive0 is selected.
When DRV is set, Drive1 is selected. The card is
selected to be Drive0 or to be Drive1 using the
Copy
field of the PC Card Socket Copy Register.
HS3-0 of the head number in CHS addressing or
LBA27-24 of the Logical Block Number in LBA
addressing.
DRV
HS3-0
LBA27-24
Status and Alternate Status Registers
The Status register and the Alternate Status register
return the card status when read by the host. Reading the
Status register clears a pending interrupt request while
reading the Alternate Status register does not. The Status
register and the Alternate Status register are read only
registers.
D7
BSY
D6
D5
DWF
D4
DSC
D3
DRQ
D2
D1
IDX
D0
ERR
DRDY
CORR
Field
BSY
function
This bit is set when the card internal operation is
executing. When this bit is set to
1
, other bits in this
register are invalid.
DRDY indicates whether the card is capable of
performing card operations.
This bit, if set, indicates a write fault has occurred.
This bit is set when the drive seek complete.
This bit is set when the information can be transferred
between the host and Data register.
This bit is set when a correctable data error has been
occurred and the data has been corrected.
This bit is always set to
0
.
This bit is set when the previous command has ended
in some type of error. The error information is set in the
other Status register bits or Error register. This bit is
cleared by the next command.
DRDY
DWF
DSC
DRQ
CORR
IDX
ERR
Command Register
The Command register contains the command code being
sent to the device. Command execution begins
immediately after this register is written. The Command
register is a write only register.
D7
D6
D5
D4
Command
D3
D2
D1
D0
Device Control Register
This register is used to control the card interrupt request
and to issue a soft reset to the card. The Device Control
register is a write only register.
D7
X
D6
X
D5
X
D4
X
D3
1
D2
D1
nIEN
D0
0
SRST
Field
X
1
SRST
function
don
t care.
This bit is set to
1
.
This bit is set to
1
in order to force the card to perform a
Command Block Reset operation. This does not change
the Card Configuration registers as a Hardware Reset
does. The card remains in Reset until this bit is reset to
0
.
This bit is used for enabling IREQ#. When this bit is set to
0
, IREQ# is enabled. When this bit is set to
1
, IREQ# is
disabled.
This bit is set to
0
.
nIEN
0
Drive Address Register
This register is provided for compatibility with the AT
disk drive interface.
D7
X
D6
D5
D4
D3
D2
D1
nDS1
D0
nDS0
nWT
G
nHS3-0
Field
X
nWTG
function
This bit is unknown.
This bit is set to
0
when a Flash write operation is in
progress, otherwise it is set to
1
.
These bits is the negative value of Head Select bits in
Drive/Head register.
This bit is set to
0
when Slave drive is active and
selected.
This bit is set to
0
when Master drive is active and
selected.
nHS3-0
nDS1
nDS0
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