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| 型号： | MIC2086-MBQS TR |
| 厂商： | Micrel Inc |
| 文件页数： | 3/29页 |
| 文件大小： | 1008K |
| 描述： | IC CTRLR HOW SWAP SGL 20-QSOP |
| 标准包装： | 2,500 |
| 类型： | 热交换控制器 |
| 应用： | 通用型 Infiniband? |
| 内部开关： | 无 |
| 电源电压： | 2.3 V ~ 16.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-SSOP（0.154"，3.90mm 宽） |
| 供应商设备封装： | 20-QSOP |
| 包装： | 带卷 (TR) |
| 其它名称： | MIC2086-MBQSTR MIC2086-MBQSTR-ND |
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Micrel, Inc.
MIC2085/2086
May 2006
3
M9999-050406
(408) 955-1690
Pin Description (Cont.)
Pin Number
MIC2086
Pin Number
MIC2085
Pin Name Pin Function
4
4
ON
ON Input: Active high. The ON pin, an input to a Schmitt-triggered comparator
used to enable/disable the controller, is compared to a V
TH
reference with
100mV of hysteresis. Once a logic high is applied to the ON pin (V
ON
> 1.24V), a
start-up sequence is initiated as the GATE pin starts ramping up towards its final
operating voltage. When the ON pin receives a low logic signal (V
ON
< 1.14V),
the GATE pin is grounded and /FAULT is high if VCC is above the UVLO
threshold. ON must be low for at least 20祍 in order to initiate a start-up
sequence. Additionally, toggling the ON pin LOW to HIGH resets the circuit
breaker.
5
5
/POR
Power-On Reset Output: Open drain N-Channel device, active low. This pin
remains asserted during start-up until a time period t
POR
after the FB pin voltage
rises above the power-good threshold (VFB). The timing capacitor CPOR
determines t
POR
. When an output undervoltage condition is detected at the FB
pin, /POR is asserted for a minimum of one timing cycle, t
POR
. The /POR pin has
a weak pull-up to VCC
6
NA
PWRGD
Power-Good Output: Open drain N-Channel device, active high. When the
voltage at the FB pin is lower than 1.24V, the PWRGD output is held low. When
the voltage at the FB pin is higher than 1.24V, then PWRGD is asserted. A pull-
up resistor connected to this pin and to VCC will pull the output up to VCC. The
PWRGD pin has a weak pull-up to VCC.
7
6
/FAULT
Circuit Breaker Fault Status Output: Open drain N-Channel device, active low.
The /FAULT pin is asserted when the circuit breaker trips due to an overcurrent
condition. Also, this pin indicates undervoltage lockout and overvoltage fault
conditions. The /FAULT pin has a weak pull-up to VCC.
8
7
FB
Power-Good Threshold Input: This input is internally compared to a 1.24V
reference with 3mV of hysteresis. An external resistive divider may be used to
set the voltage at this pin. If this input momentarily goes below 1.24V, then /POR
is activated for one timing cycle, t
POR
, indicating an output undervoltage
condition. The /POR signal de-asserts one timing cycle after the FB pin exceeds
the power-good threshold by 3mV. A 5祍 filter on this pin prevents glitches from
inadvertently activating this signal.
9, 10
8
GND
Ground Connection: Tie to analog ground
11
9
OV
OV Input: When the voltage on OV exceeds its trip threshold, the GATE pin is
pulled low and the CRWBR timer starts. If OV remains above its threshold long
enough for CRWBR to reach its trip threshold, the circuit breaker is tripped.
Otherwise, the GATE pin begins to ramp up one POR timing cycle after OV
drops below its trip threshold.
12
10
COMPOUT Uncommitted Comparators Open Drain Output.
13
11
COMP+
Comparators Non-Inverting Input.
14
12
COMP-
Comparators Inverting Input.
15
Na
DIS
Discharge Output: When the MIC2086 is turned off, a 550& internal resistor at
this output allows the discharging of any load capacitance to ground.
16
13
REF
Reference Output: 1.24V nominal. Tie a 0.1礔 capacitor to ground to ensure
stability.
17
14
GATE
Gate Drive Output: Connects to the gate of an external N-Channel MOSFET. An
internal clamp ensures that no more than 13V is applied between the GATE pin
and the source of the external MOSFET. The GATE pin is immediately brought
low when either the circuit breaker trips or an undervoltage lockout condition
occurs.
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