参数资料
型号: MIC2176-2YMM
厂商: Micrel Inc
文件页数: 16/31页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM 10-MSOP
标准包装: 100
系列: Hyper Speed Control™
PWM 型: 混合物
输出数: 1
频率 - 最大: 250kHz
占空比: 93%
电源电压: 4.5 V ~ 75 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 125°C
封装/外壳: 10-TFSOP,10-MSOP(0.118",3.00mm 宽)
包装: 管件
其它名称: 576-3757-5
I CL ≈
(3)
Micrel, Inc.
Using the typical V CL value of 130mV, the current-limit
value is roughly estimated as:
130mV
R DS(ON)
For designs where the current ripple is significant
compared to the load current I OUT , or for low duty cycle
operation, calculating the current limit I CL should take
into account that one is sensing the peak inductor
current and that there is a blanking delay of
approximately 150ns.
MIC2176
MOSFET Gate Drive
The MIC2176 high-side drive circuit is designed to
switch an N-Channel MOSFET. Figure 1 shows a
bootstrap circuit, consisting of D1 (a Schottky diode is
recommended) and C BST . This circuit supplies energy to
the high-side drive circuit. Capacitor C BST is charged
while the low-side MOSFET is on and the voltage on the
SW pin is approximately 0V. When the high-side
MOSFET driver is turned on, energy from C BST is used to
turn the MOSFET on. As the high-side MOSFET turns
on, the voltage on the SW pin increases to
approximately V IN . Diode D1 is reverse biased and C BST
floats high while continuing to keep the high-side
MOSFET on. The bias current of the high-side driver is
130mV V × T DLY
Δ I L(pp) = OUT
I CL = + OUT
R DS(ON) L
V × (1 ? D)
f SW × L
?
Δ I L(pp)
2
(4)
(5)
less than 10mA so a 0.1 μ F to 1 μ F is sufficient to hold
the gate voltage with minimal droop for the power stroke
(high-side switching) cycle, i.e. Δ BST = 10mA x
3.33 μ s/0.1 μ F = 333mV. When the low-side MOSFET is
turned back on, C BST is recharged through D1. A small
resistor R G , which is in series with C BST , can be used to
slow down the turn-on time of the high-side N-channel
where
V OUT = The output voltage
T DLY = Current-limit blanking time, 150ns typical
Δ I L(pp) = Inductor current ripple peak-to-peak value
D = Duty Cycle
f SW = Switching frequency
MOSFET.
The drive voltage is derived from the V DD supply voltage.
The nominal low-side gate drive voltage is V DD and the
nominal high-side gate drive voltage is approximately
V DD – V DIODE , where V DIODE is the voltage drop across
D1. An approximate 30ns delay between the high-side
and low-side driver transitions is used to prevent current
from simultaneously flowing unimpeded through both
MOSFETs.
The MOSFET R DS(ON) varies 30% to 40% with
temperature; therefore, it is recommended to add a 50%
margin to I CL in the above equation to avoid false current
limiting due to increased MOSFET junction temperature
rise. It is also recommended to connect SW pin directly
to the drain of the low-side MOSFET to accurately sense
the MOSFETs R DS(ON) .
November 2010
16
M9999-111710-A
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