参数资料
型号: MIC2196YM
厂商: Micrel Inc
文件页数: 10/12页
文件大小: 0K
描述: IC REG CTRLR BST FLYBK PWM 8SOIC
标准包装: 95
PWM 型: 电流模式
输出数: 1
频率 - 最大: 440kHz
占空比: 85%
电源电压: 2.9 V ~ 14 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 125°C
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
包装: 管件
产品目录页面: 1092 (CN2011-ZH PDF)
其它名称: 576-1717-5
MIC2196YM-ND
Micrel, Inc.
The enable pin (pin 3) has two threshold levels, allowing
the MIC2196 to shut down in a micro-current mode, or
turn-off output switching in standby mode. Below 0.9V,
the device is forced into a micro power shutdown. If the
enable pin is between 0.9V and 1.5V the output gate
drive is disabled but the internal circuitry is powered on
and the soft start pin voltage is forced low. There is
typically 135mV of hysteresis below the 1.5V threshold
to insure the part does not oscillate on and off due to
ripple voltage on the input. Raising the enable voltage
above the UVLO threshold of 1.5V enables the output
drivers and allows the soft start capacitor to charge. The
enable pin may be pulled up to VINA.
Oscillator and Sync
The internal oscillator is self-contained and requires no
external components. The maximum duty cycle of the
MIC2196 is 85%.
Minimum duty cycle becomes important in a boost
converter as the input voltage approaches the output
voltage. At lower duty cycles, the input voltage can be
closer to the output voltage without the output rising out
of regulation. Minimum duty cycle is typically 7%.
A frequency foldback mode is enabled if the voltage on
the feedback pin (pin 2) is less than 0.3V. In frequency
foldback the oscillator frequency is reduced by
MIC2196
Decoupling Capacitor Selection
A 1 μ F decoupling capacitor is used to stabilize the
internal regulator and minimize noise on the V DD pin.
Placement of this capacitor is critical to the proper
operation of the MIC2196. It must be next to the V DD and
signal ground pins and routed with wide etch. The
capacitor should be a good quality ceramic. Incorrect
placement of the V DD decoupling capacitor will cause
jitter and/or oscillations in the switching waveform as
well as variations in the overcurrent limit.
A minimum 1 μ F ceramic capacitor is required to
decouple the V IN . The capacitor should be placed near
the IC and connected directly between pins 8 (V CC ) and
6 (GND). For V IN greater than 8V, use a 4.7 μ F or a 10 μ F
ceramic capacitor to decouple the V DD pin.
Efficiency Calculation and Considerations
Efficiency is the ratio of output power to input power. The
difference is dissipated as heat in the boost converter.
The significant contributors at light output loads are:
? The VIN pin supply current which includes the
current required to switch the external
MOSFETs.
? Core losses in the inductor.
To maximize efficiency at light loads:
approximately a factor of 4.
Voltage Setting Components
The MIC2196 requires two resistors to set the output
voltage as shown in Figure 5.
MIC2196
?
?
Use a low gate charge MOSFET or use the
smallest MOSFET, which is still adequate for the
maximum output current.
Use a ferrite material for the inductor core, which
has less core loss than an MPP or iron power
core.
The significant contributors to power loss at higher
output loads are (in approximate order of magnitude):
Voltage
Amplifier
R1
?
?
Resistive on-time losses in the MOSFET
Switching transition losses in the MOSFET
V REF
1.245V
Pin
6
R2
?
?
?
Inductor resistive losses
Current sense resistor losses
Output capacitor resistive losses (due to the
capacitor’s ESR)
To minimize power loss under heavy loads:
V O = V REF × 1 +
Figure 5. Voltage Setting Components
The output voltage is determined by the equation below:
R1
R2
Where: V REF for the MIC2196 is nominally 1.245V.
Lower values of resistance are preferred to prevent
noise from appearing on the V FB pin. A typically
recommended value for R1 is 10K.
September 2008
10
?
?
Use logic level, low on resistance MOSFETs.
Multiplying the gate charge by the on-resistance
gives a figure of merit, providing a good balance
between switching and resistive power
dissipation.
Slow transition times and oscillations on the
voltage and current waveforms dissipate more
power during the turn-on and turn-off of the low
side MOSFET. A clean layout will minimize
parasitic inductance and capacitance in the gate
drive and high current paths. This will allow the
M9999-092908
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