参数资料
型号: MIC2586-2YM
厂商: Micrel Inc
文件页数: 16/22页
文件大小: 492K
描述: IC CTRLR/SEQUENCE HOTSWAP 14SOIC
产品培训模块: Hot-Swap High-Voltage
标准包装: 54
类型: 热交换控制器
应用: 通用
内部开关:
电源电压: 10 V ~ 80 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 14-SOIC(0.154",3.90mm 宽)
供应商设备封装: 14-SOIC
包装: 管件
产品目录页面: 1085 (CN2011-ZH PDF)
其它名称: 576-1094
icrel, Inc.
MIC2586/MIC2586R
 
 
ecember 2012
16
M9999-122012
 
Power Good (PWRGD) Output Signals
For the MIC2586-1/MIC2586R-1, the power good output
signal PWRGD1 will be high impedance when the FB pin
voltage is higher than the V
FBH
  threshold and will pull
down to GND when the FB pin voltage is lower than the
V
FBL
 threshold. For the MIC2586-2/MIC2586R-2, power-
good output signal /PWRGD1 will pull down to GND
when the FB pin voltage is higher than the V
FBH
 
threshold and will be high impedance when the FB pin
voltage is lower than the V
FBL
 threshold. Hence, the (1)
parts have an active-HIGH PWRGDx signal and the (2)
parts have an active-LOW /PWRGDx output. PWRGDx
(or /PWRGDx) may be used as an enable signal for one
or more DC/DC converter modules or for other system
functions. When used as an enable signal, the time
necessary for the PWRGDx (or /PWRGDx) signal to pull-
up (when in high impedance state) will depend upon the
(RC) load at the respective PWRGD pin.
PWRGD output signals PWRGD2 (/PWRGD2) and
PWRGD3 (/PWRGD3) are asserted after the assertion
of PWRGD1 (/PWRGD1) by a user-programmable time
delay set by an external capacitor (CPG) from the
controller's PGTIMER pin (Pin 7) to GND. An expression
for the time delay to assert PWRGD2 (or /PWRGD2)
after PWRGD1 (or /PWRGD1) asserts is given by:
 
PG2
P
PG
2)
PG(1
V
I
C
?/DIV>
=

 
Eq. 9
 
where V
PG2
  (0.625V, typically) is the PWRGD2 (or
/PWRGD2) threshold voltage for PGTIMER and I
CPG
 
(7礎, typically) is the internal PGTIMER pin charging
current. Similarly, an expression for the time delay to
assert PWRGD3 (or /PWRGD3) after PWRGD1 (or
/PWRGD1) asserts is given by:
 
PG3
P
PG
3)
PG(1
V
I
C
?/DIV>
=

 
Eq. 10
 
where V
PG3
  (1.25V, typically) is the PWRGD3 (or
/PWRGD3) threshold voltage for PGTIMER. Therefore,
PWRGD2 (or /PWRGD2) will be delayed after the
assertion of PWRGD1 (or /PWRGD1) by:
 
(礔)
C
90
(ms)
PG
2)
PG(1
?/DIV>
E

 
Eq. 11
 
PWRGD3 (/PWRGD3) follows the assertion of PWRGD1
(/PWRGD1) by a delay:
 
(礔)
C
180
(ms)
PG
3)
PG(1
?/DIV>
E

 
Eq. 12
 
For example, for a C
PG
  of 0.1礔, PWRGD2 (or
/PWRGD2) will be asserted 9ms after PWRGD1 (or
/PWRGD1). PWRGD3 (or /PWRGD3) will then be
asserted 9ms after PWRGD2 (or /PWRGD2) and 18ms
after the assertion of PWRGD1 (or /PWRGD1). The
relationships between V
OUT
, V
FBH
, PWRGD1, PWRGD2,
and PWRGD3 are shown in Figures 5 and 6.
Each PWRGD output pin is connected to an open-drain,
N-channel   transistor   implemented   with   high-voltage
structures. These transistors are capable of operating
with pull-up resistors to supply voltages as high as 100V.
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
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