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| 型号： | MIC2586R-1BM TR |
| 厂商： | Micrel Inc |
| 文件页数： | 14/22页 |
| 文件大小： | 492K |
| 描述： | IC CTRLR/SEQ HOT SWAP 14-SOIC |
| 标准包装： | 2,500 |
| 类型： | 热交换控制器 |
| 应用： | 通用 |
| 内部开关： | 无 |
| 电源电压： | 10 V ~ 80 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 14-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 14-SOIC |
| 包装： | 带卷 (TR) |
| 其它名称： | MIC2586R-1BMTR MIC2586R-1BMTR-ND |
icrel, Inc.
MIC2586/MIC2586R
ecember 2012
14
M9999-122012
The nominal current limit is determined by Equation 3:
EN E
TRIP(TYP)
LIMIT
R
V
=
Eq. 3
where V
TRIP(TYP)
is the typical current limit threshold
specified in the datasheet and R
SENSE
is the value of the
selected sense resistor. As the MIC2586 and the
MIC2586R employ a constant-current regulation scheme
in current limit, the charge pumps output voltage at the
GATE pin is adjusted so that the voltage across the
external sense resistor is held equal to V
TRIP
while the
capacitor connected to the TIMER pin is being charged.
If the current-limit condition goes away before the
TIMER pin voltage rises above the V
TIMERH
threshold,
then steady-state operation resumes. To prevent
excessive power dissipation in the external MOSFET
under load current fault conditions, the FB pin voltage is
used as the control element in a circuit that lowers the
current limit as a function of the output voltage. When
the load current increases to the point where the output
voltage at the load approaches 0V (likewise, the
MIC2586/MIC2586Rs FB pin voltage also approaches
0V), the result is a proportionate decrease in the
maximum current allowed into the load. This foldback
current limit subcircuits transfer characteristic is shown
in Figure 1. Under excessive load conditions (output and
FB voltage equals 0V), the foldback current limiting
circuit controls the MIC2586/MIC2586Rs GATE drive to
force a constant 12mV (typical) voltage drop across the
external sense resistor.
Circuit Breaker Operation
The MIC2586/MIC2586R employ an electronic circuit
breaker that protects the external N-channel power
MOSFET and other system components against large-
scale output current faults, both during initial card
insertion or during steady-state operation. The current-
limit threshold is set via an external resistor, R
SENSE
,
connected between the circuits VCC pin and SENSE
pin. For the MIC2586/MIC2586R, a fault current timing
circuit is set via an external capacitor (C
TIMER
) that
determines the length of the time delay (t
FLT
) for which
the controller remains in current limit before the circuit
breaker is tripped. Programming the response time of
the overcurrent detector helps to prevent nuisance
tripping of the circuit breaker because of high inrush
currents charging bulk and distributed capacitive loads.
The nominal overcurrent response time is calculated
using Equation 4:
(技F
C
20
(ms)
I
V
C
(ms)
FILTER
FLT
TIMERUP
TIMERH
FILTER
FLT
?/DIV>
=
?/DIV>
=
Eq. 4
Whenever the voltage across R
SENSE
exceeds the
MIC2586/MIC2586Rs nominal circuit breaker threshold
voltage of 47mV during steady-state operation, two
things occur:
1. A constant-current regulation loop will engage within
1祍 after an overcurrent condition is detected by
R
SENSE
, and the control loop is designed to hold the
voltage across R
SENSE
equal to 47mV. This feature
protects both the load and the MIC2586/MIC2586R
circuits from excessively high currents.
2. Capacitor C
TIMER
is then charged up to the V
TIMERH
threshold (1.313V) by an internal 65礎 current
source (I
TIMERUP
). If the excessive current persists
such that the voltage across C
TIMER
crosses the
V
TIMERH
threshold, the circuit breaker trips and the
GATE pin is immediately pulled low by a 30mA
(minimum) internal current sink. This operation turns
off the MOSFET quickly and disconnects the input
from the load. The value of C
TIMER
should be
selected to allow the circuit's minimum regulated
output current (I
OUT
) to equal I
LIMIT
for somewhat
longer than the time it takes to charge the total load
capacitance.
An initial value for C
TIMER
is found by calculating the time
it will take for the MIC2586/MIC2586R to completely
charge up the output capacitive load. Assuming the load
is enabled by the PWRGDx (or /PWRGDx) signal(s) of
the controller, the turn-on delay time is derived from the
following expression, I = C ?(dV/dt):
LIMIT
CC(MAX)
LOAD
ON
-
TURN
I
V
C
?/DIV>
=
Eq. 5
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