参数资料
型号: MIC2810-4LSYML TR
厂商: Micrel Inc
文件页数: 14/18页
文件大小: 508K
描述: IC REG TRPL BUCK/LINEAR 16-MLF
标准包装: 1
拓扑: 降压(降压)(1),线性(LDO)(2)
功能: 任何功能
输出数: 3
频率 - 开关: 2MHz
电压/电流 - 输出 1: 1.2V,600mA
电压/电流 - 输出 2: 2.7V,300mA
电压/电流 - 输出 3: 3.3V,300mA
带 LED 驱动器:
带监控器:
带序列发生器:
电源电压: 1.65 V ~ 5.5 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 16-VFQFN,16-MLF?
供应商设备封装: 16-MLF?(4x4)
包装: 标准包装
产品目录页面: 1086 (CN2011-ZH PDF)
其它名称: 576-2708-6
Micrel, Inc.
MIC2810
 
 
February 2008 
14
M9999-022008-C
 
SW
The switch (SW) pin connects directly to the inductor
and provides the switching current necessary to operate
in PWM mode. Due to the high speed switching on this
pin, the switch node should be routed away from
sensitive nodes.
PGND
Power ground (PGND) is the ground path for the high
current PWM mode. The current loop for the power
ground should be as small as possible.
SGND
Signal ground (SGND) is the ground path for the biasing
and control circuitry. The current loop for the signal
ground should be as small as possible.
CSET
The CSET pin is a current source output that charges a
capacitor that sets the delay time for the power-on reset
output from low to high. The delay for POR high to low
(detecting an undervoltage on any of the outputs) is
always minimal. The current source of 1.25礎 charges a
capacitor up from 0V. When the capacitor reaches
1.25V, the output of the POR is allowed to go high. The
delay time in microseconds is equal to the Cset in
picofarads.
POR Delay (祍) = CSET (pF)
Component Selection
Output Capacitor
LDO1 and LDO2 outputs require a 2.2礔 ceramic output
capacitor for stability. The DC/DC switch mode regulator
also requires a 2.2礔 ceramic output capacitor to be
stable. All output capacitor values can be increased to
improve transient response, but performance has been
optimized for a 2.2礔 ceramic on the LDOs and the
DC/DC regulator. X7R/X5R dielectric-type ceramic
capacitors are recommended because of their
temperature performance. X5R/X7R-type capacitors
change capacitance by 15% over their operating
temperature range and are the most stable type of
ceramic capacitors. Z5U and Y5V dielectric capacitors
change value by as much as 50% to 60% respectively
over their operating temperature ranges.
Input Capacitor
A minimum 1礔 ceramic, 4.7礔 recommended, should
be placed as close as possible to the VIN pin for optimal
bypassing. X5R or X7R dielectrics are recommended for
the input capacitor. Y5V dielectrics lose most of their
capacitance over temperature and are therefore, not
recommended. A minimum 1礔 is recommended close
to the VIN and PGND pins for high frequency filtering.
Smaller case size capacitors are recommended due to
their lower ESR and ESL. Please refer to the PCB layout
section for an example of an appropriate circuit layout.
Inductor Selection
The MIC2810 is designed for use with a 2.2礖 inductor.
Proper selection should ensure the inductor can handle
the maximum average and peak currents required by the
load. Maximum current ratings of the inductor are
generally given in two methods; permissible DC current
and saturation current. Permissible DC current can be
rated either for a 40癈 temperature rise or a 10% to 20%
loss in inductance. Ensure that the inductor selected can
handle the maximum operating current. When saturation
current is specified, make sure that there is enough
margin that the peak current will not saturate the
inductor. Peak inductor current can be calculated as
follows:
L
f
2
V
V
1
V
I
I
IN
OUT
OUT
OUT
PK
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>

+
=
 
I
PK
:   Peak Inductor Current
I
OUT
:   Output/Load Current
V
IN
:   Input Voltage
V
OUT
: Output Voltage
f:    Switching Frequency of PWM Regulator
L:    Inductor Value
 
 
 
 
 
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