参数资料
型号: MIC3263YML TR
厂商: Micrel Inc
文件页数: 17/32页
文件大小: 0K
描述: IC LED DRIVER 6CH BKLT 24-MLF
特色产品: MIC3263 Boost Switching Regulator
标准包装: 1
恒定电流:
拓扑: PWM,升压(升压)
输出数: 6
内部驱动器:
类型 - 主要: 背光
类型 - 次要: 白色 LED
频率: 400kHz ~ 1.8MHz
电源电压: 6 V ~ 40 V
安装类型: 表面贴装
封装/外壳: 24-VFQFN 裸露焊盘,24-MLF?
供应商设备封装: 24-MLF?(4x4)
包装: 标准包装
工作温度: -40°C ~ 125°C
其它名称: 576-3663-6
MIC3263YML TRDKR
MIC3263YML TRDKR-ND
Micrel, Inc.
VDD
This is the output of the internal LDO regulator. Connect a
10 μ F cerami c capacitor to this pin.
PWM Dimming
The duty cycle of the PWM pulse applied to th e DRC input
is converted to 16 log levels. This logarithmic d imming is a
unique feature of the MIC3263 which better matches the
sensitivity of the human eye compared to linear dimming.
The DRC duty-cyc le to DR duty-cycle con version is s hown
in T ab le 2 .
MIC3263
DR = 10 ?
Dim Ratio = PWMD
LEDON
N
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
DR C Duty
C ycle
%
0
6.25
12.5
18.75
25
31.25
37.5
43.75
50
56.25
62.5
68.75
75
81.25
87.5
93.75
P WM Dimming Ratio (DR)
(N 1) / 7
%
0
1.0
1.4
1.9
2.7
3.7
5.2
7.2
10
14
19
27
37
52
72
100
Figure 7. Duty-Cycle Thresholds and Hysteresis
PWM Dimming Limits
The minimum pulse width of the PWM Dim is determined
by the PWM Dimming frequency and the L and C used in
the boost stages output filter. At low-PWM Dimming
frequencies, higher dimming ratios can be achieved:
T
T
Figure 8. PWM Dimming Ratio
Consider that the human eye will perceive light flicker at a
Table 2. Dimming Ratio
To avoid skipping between dimming levels, the MIC3263
uses Flicker-Free Dimming control. This techniq ue uses a
PWM dimming frequency below 1 00Hz. At 100Hz the time
between pulses is 10 μ s. If the PWM dimming minimum
pulse width is 5 μ s, then:
digital filter and hysteresis on the DRC pulse to provide a
clean DR output. The digital filter has a 0.1 μ F capacitor on
the CINT pin to average the duty cycles of the PWM
pulses. The averaged duty cycle has to be 4.16% higher
Dim Ratio =
10ms
5 μ s
= 2000/1
than the nominal value before moving to the next dimming
level as shown in Figure 7. Likewise, to move the previous
dimming level the duty cycle has to be ? 4.16% lower than
the nominal. To prevent flicker the duty-cycle hysteresis is
set a 2%.
If high dimming ratios are required, a lower dimming
frequency is required. During each DR pulse, the inductor
current has to ramp up to it steady state value to generate
the necessary boost output voltage in order for the full
programmed LED current to flow in the LED channels. The
smaller the inductance value the faster this time is and a
narrower PWM dimming pulse can be achieved. But
smaller inductance means higher ripple current.
January 2010
17
M9999-012110
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