参数资料
| 型号： | MIC4721YMMTR |
| 厂商： | Micrel Inc |
| 文件页数： | 8/19页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK ADJ 1.5A 10MSOP |
| 标准包装： | 2,500 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 可调至 1V |
| 输入电压： | 2.7 V ~ 5.5 V |
| 频率 - 开关： | 2MHz |
| 电流 - 输出： | 1.5A |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-TFSOP，10-MSOP（0.118"，3.00mm 宽） |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 10-MSOP |
| 其它名称： | MIC4721YMM TR |
Micrel, Inc.
Pin Descriptions
VIN
Two pins for VIN provide power to the source of the
internal P-channel MOSFET along with the current
limiting sensing. The VIN operating voltage range is from
2.7V to 5.5V. Due to the high switching speeds, a 10μF
capacitor should be placed close to VIN and power
ground (PGND) at each pin for bypassing. Please refer
to the section on layout recommendations.
BIAS
The bias (BIAS) provides power to the internal reference
and control sections of the MIC4721. A 10 ? resistor
from VIN to BIAS and a 0.1μF from BIAS to SGND is
required.
EN
The enable pin provides a logic level control of the
output. At a low level, the output is shut off and supply
current at the VIN pin is greatly reduced (typically <2μA).
A high level turns the output on. The enable pin must not
be driven above the supply voltage.
FB
The feedback pin (FB) connects to the negative input of
the internal error amplifier. The pin is connected to an
external resistor divider, which sets the output voltage.
A feedforward capacitor across the upper resistor in the
divider is recommended for most designs. To reduce
current draw, a 10K feedback resistor is recommended
from the output to the FB pin (R1). The large resistor
value and the parasitic capacitance of the FB pin can
cause a high frequency pole that can reduce the overall
system phase margin. By placing a feedforward
capacitor, these effects can be significantly reduced.
MIC4721
SW
The switch (SW) pin connects directly to the inductor
and provides the switching current necessary to operate
in PWM mode. Due to the high speed switching on this
pin, the switch node should be routed away from
sensitive nodes. This pin also connects to the cathode of
the free-wheeling diode.
PGOOD
The power good pin pulls low to indicate the output
voltage is within its regulation range. When power good
is low, then the output voltage is within ±10% of the set
regulation voltage. For output voltages greater or less
than 10%, the PGOOD pin is high. This should be
connected to the input supply through a pull up resistor.
A delay can be added by placing a capacitor from
PGOOD-to-ground.
PGND
Power ground (PGND) is the ground path for the
MOSFET drive current. The current loop for the power
ground should be as small as possible and separate
from the Signal ground (SGND) loop. Refer to the
section on layout recommendations for more details.
SGND
Signal ground (SGND) is the ground path for the biasing
and control circuitry. The current loop for the signal
ground should be separate from the power ground
(PGND) loop. Refer to the section on layout
recommendations for more details.
May 2007
8
M9999-052907-A
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