参数资料
| 型号： | MIC5373-MG4YMT TR |
| 厂商： | Micrel Inc |
| 文件页数： | 16/22页 |
| 文件大小： | 0K |
| 描述： | IC REG LDO 2.8V/1.8V/1.2V 16MLF |
| 标准包装： | 1 |
| 稳压器拓扑结构： | 正，固定式 |
| 输出电压： | 2.8V，1.8V，1.2V |
| 输入电压： | 1.7 V ~ 5.5 V |
| 电压 - 压降（标准）： | 0.17V @ 150mA，0.275V @ 150mA，0.275V @ 150mA |
| 稳压器数量： | 3 |
| 电流 - 输出： | 150mA |
| 电流 - 限制（最小）： | 200mA |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-UFQFN 裸露焊盘，16-MLF? |
| 供应商设备封装： | 16-MLF（2.5x2.5） |
| 包装： | 标准包装 |
| 其它名称： | 576-3911-6 |
Micrel, Inc.
Pin Descriptions
INLDO
The LDO input pins INLDO1/2 and INLDO3 provide the
input power to the linear regulators LDO1, LDO2 and
LDO3. The input operating voltage range is from 1.7V to
5.5V. For input voltages from 1.7V to 2.5V the output
current must be limited to 30mA each. Due to line
inductance a 1μF capacitor placed close to the INLDO
pins and the GND pin is recommended. Please refer to
layout recommendations.
BIAS
The BIAS pin provides power to the internal reference
and control sections of the MIC5373/83. A 0.1μF
ceramic capacitor must be connected from BIAS to GND
for clean operation.
EN (MIC5373)
The enable (EN) pins EN1, EN2 and EN3 provide logic
level control for the outputs OUT1, OUT2 and OUT3,
respectively. A logic high signal on an enable pin
activates the respective LDO. A logic low signal on an
enable pin deactivates the respective LDO. Do not leave
the EN pins floating, as it would leave the regulator in an
unknown state.
/EN (MIC5383)
The enable (EN) pins /EN1, /EN2 and /EN3 provide logic
level control for the outputs OUT1, OUT2 and OUT3,
respectively. A logic high signal on an enable pin
MIC5373/83
A delay can be added by placing a capacitor from the
DLY pin to ground.
POR_IN
The power-on-reset input (POR_IN) pin compares any
voltage to an internal 0.9V reference. This function can
be used to monitor any of the LDO outputs or any
external voltage rail. When the monitored voltage is
greater than 0.9V, the POR_IN flag will internally trigger
a 1.25μA source current to charge the external capacitor
at the DLY pin. A resistor divider network may be used
to divide down the monitored voltage to be compared
with the 0.9V at the POR_IN. This resistor network can
change the trigger point to any voltage level. A small
decoupling capacitor is recommended between POR_IN
and ground to reject high frequency noise that might
interfere with the POR circuit. Do not leave the POR_IN
pin floating.
DLY
The delay (DLY) pin is used to set the POR delay time.
Adding a capacitor to this pin adjusts the delay of the
POR signal. When the POR_IN flag is triggered, a
constant 1.25μA current begins to charge the external
capacitor tied to the DLY pin. When the capacitor
reaches 1.25V the POR will be pulled high by the
external pull up resistor. Equation 1 illustrates how to
calculate the charge time is shown:
t DELAY (s) = ? ?
? ?
deactivates the respective LDO. A logic low signal on an
enable pin activates the respective LDO. Do not leave
the EN pins floating, as it would leave the regulator in an
? 1.25V x C DLY
? 1 . 25 x 10 ? 6
?
?
Eq. 1
unknown state.
OUT
OUT1, OUT2 and OUT3 are the output pins of each
LDO. A minimum of 1μF capacitor be placed as close as
possible to each of the OUT pins. A minimum voltage
rating of 6.3V is recommended for each capacitor.
GND
The ground (GND) pin is the ground path for the control
circuitry and the power ground for all LDOs. The current
loop for the ground should be kept as short as possible.
Refer to the layout recommendations for more details.
POR
The power-on-reset (POR) pin is an open drain output. A
resistor (10k ? to 100k ? ) can be used for a pull up to
either the input or the output voltage of the regulator.
POR is asserted high when the voltage at DLY reaches
1.25V.
The delay time (t) is in seconds, the delay voltage is
1.25V internally, and the external delay capacitance
(C DLY ) is in microfarads. For a 1μF delay capacitor, the
delay time will be 1 second. A capacitor at the DLY pin is
recommended when the POR function is used in order to
prevent unexpected triggering of the POR signal in noisy
systems.
MR
The manual reset (MR) pin resets the output of POR and
DLY generator regardless if the monitored voltage is in
regulation or not. Applying a voltage greater than 1.2V
on the MR pin will cause the POR voltage to be pulled
low. When a voltage below 0.2V is applied to the MR
pin, the internal 1.25μA will begin to charge the DLY pin
until it reaches 1.25V. When the DLY pin reaches
1.25V, the POR voltage will be pulled high by the pull up
external resistor again. Do not leave the MR pin floating.
September 2012
16
M9999-091712
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| MIC5373-SJGYMT TR | 功能描述:低压差稳压器 - LDO Triple 200mA LDO w/User Defined Voltage Monitoring RoHS:否 制造商:Texas Instruments 最大输入电压:36 V 输出电压:1.4 V to 20.5 V 回动电压（最大值）:307 mV 输出电流:1 A 负载调节:0.3 % 输出端数量: 输出类型:Fixed 最大工作温度:+ 125 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-20 |
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